wifi: rtw89: mac: set bfee_ctrl() according to chip gen
authorZong-Zhe Yang <kevin_yang@realtek.com>
Thu, 12 Oct 2023 02:14:53 +0000 (10:14 +0800)
committerKalle Valo <kvalo@kernel.org>
Sat, 14 Oct 2023 06:43:32 +0000 (09:43 +0300)
When associated peer has beamformer capability, enable hardware beamformee
function, and then hardware can run sounding protocol itself. Oppositely,
disable this function when disassociated. Define different registers for
WiFi 6 and 7 generations respectively.

Signed-off-by: Zong-Zhe Yang <kevin_yang@realtek.com>
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20231012021455.19816-5-pkshih@realtek.com
drivers/net/wireless/realtek/rtw89/mac.c
drivers/net/wireless/realtek/rtw89/mac.h
drivers/net/wireless/realtek/rtw89/mac_be.c
drivers/net/wireless/realtek/rtw89/reg.h

index d2621f31a78a8635c3787b34632bf8e9d53f92ad..b47b3c9be2cb3be374d8c69611eb84346c040db4 100644 (file)
@@ -5210,12 +5210,12 @@ static void rtw89_mac_bfee_standby_timer(struct rtw89_dev *rtwdev, u8 mac_idx,
 
 static void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en)
 {
+       const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
        u32 reg;
-       u32 mask = B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN |
-                  B_AX_BFMEE_HE_NDPA_EN;
+       u32 mask = mac->bfee_ctrl.mask;
 
        rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en);
-       reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx);
+       reg = rtw89_mac_reg_by_idx(rtwdev, mac->bfee_ctrl.addr, mac_idx);
        if (en) {
                set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags);
                rtw89_write32_set(rtwdev, reg, mask);
@@ -5759,6 +5759,11 @@ const struct rtw89_mac_gen_def rtw89_mac_gen_ax = {
                .addr = R_AX_MUEDCA_EN,
                .mask = B_AX_MUEDCA_EN_0 | B_AX_SET_MUEDCATIMER_TF_0,
        },
+       .bfee_ctrl = {
+               .addr = R_AX_BFMEE_RESP_OPTION,
+               .mask = B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN |
+                       B_AX_BFMEE_HE_NDPA_EN,
+       },
 
        .disable_cpu = rtw89_mac_disable_cpu_ax,
        .fwdl_enable_wcpu = rtw89_mac_enable_cpu_ax,
index 982b357ec6f1db4ecb8446dd318985062ac2f029..6c043259c5e08429dfd2a3446ce63933ee748c06 100644 (file)
@@ -862,6 +862,7 @@ struct rtw89_mac_gen_def {
        u32 agg_len_ht;
 
        struct rtw89_reg_def muedca_ctrl;
+       struct rtw89_reg_def bfee_ctrl;
 
        void (*disable_cpu)(struct rtw89_dev *rtwdev);
        int (*fwdl_enable_wcpu)(struct rtw89_dev *rtwdev, u8 boot_reason,
index 514cf566eba19d13809f41104dda62356b9fd2b9..7cf67020c6e66abb2d6362b19ad0c6d6d930f055 100644 (file)
@@ -256,6 +256,11 @@ const struct rtw89_mac_gen_def rtw89_mac_gen_be = {
                .addr = R_BE_MUEDCA_EN,
                .mask = B_BE_MUEDCA_EN_0 | B_BE_SET_MUEDCATIMER_TF_0,
        },
+       .bfee_ctrl = {
+               .addr = R_BE_BFMEE_RESP_OPTION,
+               .mask = B_BE_BFMEE_HT_NDPA_EN | B_BE_BFMEE_VHT_NDPA_EN |
+                       B_BE_BFMEE_HE_NDPA_EN | B_BE_BFMEE_EHT_NDPA_EN,
+       },
 
        .disable_cpu = rtw89_mac_disable_cpu_be,
        .fwdl_enable_wcpu = rtw89_mac_fwdl_enable_wcpu_be,
index d62b3f93b14ecaaa7b998b1394b637447ceafdbd..aee54859f92bab57c66e8d5c4f38b08cc4c56cce 100644 (file)
 #define B_BE_UPD_HGQMD BIT(1)
 #define B_BE_UPD_TIMIE BIT(0)
 
+#define R_BE_BFMEE_RESP_OPTION 0x11180
+#define R_BE_BFMEE_RESP_OPTION_C1 0x15180
+#define B_BE_BFMEE_CSI_SEC_TYPE_SH 20
+#define B_BE_BFMEE_CSI_SEC_TYPE_MSK 0xf
+#define B_BE_BFMEE_BFRPT_SEG_SIZE_SH 16
+#define B_BE_BFMEE_BFRPT_SEG_SIZE_MSK 0x3
+#define B_BE_BFMEE_MIMO_EN_SEL BIT(8)
+#define B_BE_BFMEE_MU_BFEE_DIS BIT(7)
+#define B_BE_BFMEE_CHECK_RPTPOLL_MACID_DIS BIT(6)
+#define B_BE_BFMEE_NOCHK_BFPOLL_BMP BIT(5)
+#define B_BE_BFMEE_VHTBFRPT_CHK BIT(4)
+#define B_BE_BFMEE_EHT_NDPA_EN BIT(3)
+#define B_BE_BFMEE_HE_NDPA_EN BIT(2)
+#define B_BE_BFMEE_VHT_NDPA_EN BIT(1)
+#define B_BE_BFMEE_HT_NDPA_EN BIT(0)
+
 #define R_BE_RX_FLTR_OPT 0x11420
 #define R_BE_RX_FLTR_OPT_C1 0x15420
 #define B_BE_UID_FILTER_MASK GENMASK(31, 24)