clk: qcom: videocc-sm8450: Set delay for Venus CLK resets

Some Venus resets may require more time when toggling. Describe that.

The value is known for SM8450, see [1].

[1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/commit/d0730ea5867264ee50b793f6700eb6a376ddcbbb

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-17-c37eba13b5ce@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/drivers/clk/qcom/videocc-sm8450.c b/drivers/clk/qcom/videocc-sm8450.c
index 16a61146e61957218f5079e3a7565bca300322e0..67ca302a0737d00c7dda7a7d291ad2f5b205eb3f 100644 (file)
--- a/drivers/clk/qcom/videocc-sm8450.c
+++ b/drivers/clk/qcom/videocc-sm8450.c
@@ -373,8 +373,8 @@ static const struct qcom_reset_map video_cc_sm8450_resets[] = {
        [CVP_VIDEO_CC_MVS0C_BCR] = { 0x8048 },
        [CVP_VIDEO_CC_MVS1_BCR] = { 0x80bc },
        [CVP_VIDEO_CC_MVS1C_BCR] = { 0x8070 },
-       [VIDEO_CC_MVS0C_CLK_ARES] = { 0x8064, 2 },
-       [VIDEO_CC_MVS1C_CLK_ARES] = { 0x808c, 2 },
+       [VIDEO_CC_MVS0C_CLK_ARES] = { .reg = 0x8064, .bit = 2, .udelay = 1000 },
+       [VIDEO_CC_MVS1C_CLK_ARES] = { .reg = 0x808c, .bit = 2, .udelay = 1000 },
 };
 
 static const struct regmap_config video_cc_sm8450_regmap_config = {