clocksource: timer-riscv: Increase rating of clock_event_device for Sstc
authorAnup Patel <apatel@ventanamicro.com>
Mon, 10 Jul 2023 13:19:02 +0000 (18:49 +0530)
committerPalmer Dabbelt <palmer@rivosinc.com>
Wed, 1 Nov 2023 02:15:49 +0000 (19:15 -0700)
When Sstc is available the RISC-V timer clock_event_device should be
the preferred clock_event_device hence we increase clock_event_device
rating for Sstc.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Link: https://lore.kernel.org/r/20230710131902.1459180-3-apatel@ventanamicro.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
drivers/clocksource/timer-riscv.c

index f2ea2b3d2d43e0327a71d570bb81f34964dd2bbe..9c8f3e2decc22c9dd48ed0fcd5b42c47a6e35ccc 100644 (file)
@@ -105,6 +105,8 @@ static int riscv_timer_starting_cpu(unsigned int cpu)
        ce->irq = riscv_clock_event_irq;
        if (riscv_timer_cannot_wake_cpu)
                ce->features |= CLOCK_EVT_FEAT_C3STOP;
+       if (static_branch_likely(&riscv_sstc_available))
+               ce->rating = 450;
        clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff);
 
        enable_percpu_irq(riscv_clock_event_irq,