drm/amd/display: Only update FP2 for full updates

[Why]
FP2 is not double buffered and must wait for VACTIVE
before programming.

[How]
Only update when there is a full update we should
change FP2 to avoid delay every flip.

Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 58eb0d69873a6225698486a1038ed58d085d502f..7339d9855ec8cc770863b959c6f84130a0815d02 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2625,6 +2625,26 @@ static void commit_planes_for_stream(struct dc *dc,
                }
        }
 
+       if (update_type != UPDATE_TYPE_FAST) {
+               // If changing VTG FP2: wait until back in vactive to program FP2
+               // Need to ensure that pipe unlock happens soon after to minimize race condition
+               for (i = 0; i < dc->res_pool->pipe_count; i++) {
+                       struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+
+                       if (pipe_ctx->top_pipe || pipe_ctx->stream != stream)
+                               continue;
+
+                       if (!pipe_ctx->update_flags.bits.global_sync)
+                               continue;
+
+                       pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK);
+                       pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);
+
+                       pipe_ctx->stream_res.tg->funcs->set_vtg_params(
+                                       pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true);
+               }
+       }
+
        if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock)
                dc->hwss.interdependent_update_lock(dc, context, false);
        else

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 52bdbf2d50f5d6fa9fb94d56b3dfee3aab4c014f..cba3c8cd12a14744eae922abcbd486f96daf59b6 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1214,17 +1214,6 @@ void dcn20_pipe_control_lock(
                !flip_immediate)
            dcn20_setup_gsl_group_as_lock(dc, pipe, false);
 
-
-       // If changing VTG FP2: wait until back in vactive to program FP2
-       // Need to ensure that pipe unlock happens soon after to minimize race condition
-       if (!lock && pipe->update_flags.bits.global_sync) {
-               pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VBLANK);
-               pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VACTIVE);
-
-               pipe->stream_res.tg->funcs->set_vtg_params(
-                               pipe->stream_res.tg, &pipe->stream->timing, true);
-       }
-
        if (pipe->stream && should_use_dmub_lock(pipe->stream->link)) {
                union dmub_hw_lock_flags hw_locks = { 0 };
                struct dmub_hw_lock_inst_flags inst_flags = { 0 };