drm/amd/display: Move AllowDRAMSelfRefreshOrDRAMClockChangeInVblank to bounding box

[Why]
This is a global parameter, not a per pipe parameter and it's useful
for experimenting with the prefetch schedule to be adjustable from
the SOC bb.

[How]
Add a parameter to the SOC bb, default is the existing policy for
all DCN. Fill it in when filling SOC bb parameters.

Revert the policy to use MinDCFClk at the same time since that's not
going to give us P-State in most cases on the spreadsheet.

Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1403
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <Daniel.Wheeler@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index 8b39a38dae3d72d82b18d02f0e2d1244a7278ef5..a0de309475a97950a58052791f10c19d973c286b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -92,7 +92,7 @@
 #define DC_LOGGER_INIT(logger)
 
 struct _vcs_dpi_ip_params_st dcn3_0_ip = {
-       .use_min_dcfclk = 1,
+       .use_min_dcfclk = 0,
        .clamp_min_dcfclk = 0,
        .odm_capable = 1,
        .gpuvm_enable = 0,

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
index e1a961a62addba7737fd1e29dd3dce4636b0d1ca..e3d9f1decdfc70b0d2e79bac00902f0401950fb5 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
@@ -3644,8 +3644,7 @@ static double TruncToValidBPP(
 void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib)
 {
        struct vba_vars_st *v = &mode_lib->vba;
-       int MinPrefetchMode = 0;
-       int MaxPrefetchMode = 2;
+       int MinPrefetchMode, MaxPrefetchMode;
        int i;
        unsigned int j, k, m;
        bool   EnoughWritebackUnits = true;
@@ -3657,6 +3656,10 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 
        /*MODE SUPPORT, VOLTAGE STATE AND SOC CONFIGURATION*/
 
+       CalculateMinAndMaxPrefetchMode(
+               mode_lib->vba.AllowDRAMSelfRefreshOrDRAMClockChangeInVblank,
+               &MinPrefetchMode, &MaxPrefetchMode);
+
        /*Scale Ratio, taps Support Check*/
 
        v->ScaleRatioAndTapsSupport = true;

diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index 73f5be26abc4dbebbfa74a01d30fda6b5050a8f8..0fad15020c74011fa9334239cfab29ba3491623a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -244,6 +244,8 @@ static void fetch_socbb_params(struct display_mode_lib *mode_lib)
        mode_lib->vba.DRAMClockChangeSupportsVActive = !soc->disable_dram_clock_change_vactive_support ||
                        mode_lib->vba.DummyPStateCheck;
        mode_lib->vba.AllowDramClockChangeOneDisplayVactive = soc->allow_dram_clock_one_display_vactive;
+       mode_lib->vba.AllowDRAMSelfRefreshOrDRAMClockChangeInVblank =
+               soc->allow_dram_self_refresh_or_dram_clock_change_in_vblank;
 
        mode_lib->vba.Downspreading = soc->downspread_percent;
        mode_lib->vba.DRAMChannelWidth = soc->dram_channel_width_bytes;   // new!
@@ -733,8 +735,6 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib)
                                                mode_lib->vba.OverrideHostVMPageTableLevels;
        }
 
-       mode_lib->vba.AllowDRAMSelfRefreshOrDRAMClockChangeInVblank = dm_try_to_allow_self_refresh_and_mclk_switch;
-
        if (mode_lib->vba.OverrideGPUVMPageTableLevels)
                mode_lib->vba.GPUVMMaxPageTableLevels = mode_lib->vba.OverrideGPUVMPageTableLevels;