arm64: dts: qcom: ipq5332: populate the opp table based on the eFuse

IPQ53xx have different OPPs available for the CPU based on
SoC variant. This can be determined through use of an eFuse
register present in the silicon.

Add support to read the eFuse and populate the OPPs based on it.

	------------------------------------------------
	Frequency	BIT2	BIT1	opp-supported-hw
			1.1GHz	1.5GHz
	------------------------------------------------
	1100000000	1	1	0x7
	1500000000	0	1	0x3
	------------------------------------------------

Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/463f01759cedef3121767d2432aa415794036ce1.1697781921.git.quic_varada@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
index d3fef2f80a81f4c545be584777debd751418b34c..5a71cfccb8e0dbcdc84679a63d595ce9e3b9a761 100644 (file)
--- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
@@ -91,11 +91,19 @@
        };
 
        cpu_opp_table: opp-table-cpu {
-               compatible = "operating-points-v2";
+               compatible = "operating-points-v2-kryo-cpu";
                opp-shared;
+               nvmem-cells = <&cpu_speed_bin>;
 
-               opp-1488000000 {
-                       opp-hz = /bits/ 64 <1488000000>;
+               opp-1100000000 {
+                       opp-hz = /bits/ 64 <1100000000>;
+                       opp-supported-hw = <0x7>;
+                       clock-latency-ns = <200000>;
+               };
+
+               opp-1500000000 {
+                       opp-hz = /bits/ 64 <1500000000>;
+                       opp-supported-hw = <0x3>;
                        clock-latency-ns = <200000>;
                };
        };
@@ -163,6 +171,11 @@
                        reg = <0x000a4000 0x721>;
                        #address-cells = <1>;
                        #size-cells = <1>;
+
+                       cpu_speed_bin: cpu-speed-bin@1d {
+                               reg = <0x1d 0x2>;
+                               bits = <7 2>;
+                       };
                };
 
                rng: rng@e3000 {