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arm64: dts: qcom: qdu1000: Add LLCC/system-cache-controller
author
Komal Bajaj
<quic_kbajaj@quicinc.com>
Mon, 13 Mar 2023 12:57:31 +0000
(18:27 +0530)
committer
Bjorn Andersson
<andersson@kernel.org>
Tue, 4 Apr 2023 19:27:27 +0000
(12:27 -0700)
Add a DT node for Last level cache (aka. system cache) controller
which provides control over the last level cache present on QDU1000
and QRU1000 SoCs.
Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link:
https://lore.kernel.org/r/20230313125731.17745-1-quic_kbajaj@quicinc.com
arch/arm64/boot/dts/qcom/qdu1000.dtsi
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diff --git
a/arch/arm64/boot/dts/qcom/qdu1000.dtsi
b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
index 99d784085fb34a9e8250222f479918144c99ef41..734438113bbae71a57472f1ed20023717bd6df6d 100644
(file)
--- a/
arch/arm64/boot/dts/qcom/qdu1000.dtsi
+++ b/
arch/arm64/boot/dts/qcom/qdu1000.dtsi
@@
-1321,6
+1321,18
@@
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
};
+
+ system-cache-controller@19200000 {
+ compatible = "qcom,qdu1000-llcc";
+ reg = <0 0x19200000 0 0xd80000>,
+ <0 0x1a200000 0 0x80000>,
+ <0 0x221c8128 0 0x4>;
+ reg-names = "llcc_base",
+ "llcc_broadcast_base",
+ "multi_channel_register";
+ interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+ multi-ch-bit-off = <24 2>;
+ };
};
timer {