drm/amd/display: Add missing dcn35 RCO registers

[Why]
Some registers needed for root clock gating in dcn35 are not defined in
the dccg header.

[How]
Add the needed registers and temporarily disable some register writes
that are now taking place successfully until the registers can be
properly enabled.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Daniel Miess <daniel.miess@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
index 76da59d8caaf545bc2815a6a464cc249fbbee7c0..ef5c22f41563d3e1c4f3d236506c153d8398e34c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
@@ -296,6 +296,38 @@
        type DTBCLK_P1_GATE_DISABLE;\
        type DTBCLK_P2_GATE_DISABLE;\
        type DTBCLK_P3_GATE_DISABLE;\
+       type DSCCLK0_ROOT_GATE_DISABLE;\
+       type DSCCLK1_ROOT_GATE_DISABLE;\
+       type DSCCLK2_ROOT_GATE_DISABLE;\
+       type DSCCLK3_ROOT_GATE_DISABLE;\
+       type SYMCLKA_FE_ROOT_GATE_DISABLE;\
+       type SYMCLKB_FE_ROOT_GATE_DISABLE;\
+       type SYMCLKC_FE_ROOT_GATE_DISABLE;\
+       type SYMCLKD_FE_ROOT_GATE_DISABLE;\
+       type SYMCLKE_FE_ROOT_GATE_DISABLE;\
+       type DPPCLK0_ROOT_GATE_DISABLE;\
+       type DPPCLK1_ROOT_GATE_DISABLE;\
+       type DPPCLK2_ROOT_GATE_DISABLE;\
+       type DPPCLK3_ROOT_GATE_DISABLE;\
+       type HDMISTREAMCLK0_ROOT_GATE_DISABLE;\
+       type SYMCLKA_ROOT_GATE_DISABLE;\
+       type SYMCLKB_ROOT_GATE_DISABLE;\
+       type SYMCLKC_ROOT_GATE_DISABLE;\
+       type SYMCLKD_ROOT_GATE_DISABLE;\
+       type SYMCLKE_ROOT_GATE_DISABLE;\
+       type PHYA_REFCLK_ROOT_GATE_DISABLE;\
+       type PHYB_REFCLK_ROOT_GATE_DISABLE;\
+       type PHYC_REFCLK_ROOT_GATE_DISABLE;\
+       type PHYD_REFCLK_ROOT_GATE_DISABLE;\
+       type PHYE_REFCLK_ROOT_GATE_DISABLE;\
+       type DPSTREAMCLK0_ROOT_GATE_DISABLE;\
+       type DPSTREAMCLK1_ROOT_GATE_DISABLE;\
+       type DPSTREAMCLK2_ROOT_GATE_DISABLE;\
+       type DPSTREAMCLK3_ROOT_GATE_DISABLE;\
+       type DPSTREAMCLK0_GATE_DISABLE;\
+       type DPSTREAMCLK1_GATE_DISABLE;\
+       type DPSTREAMCLK2_GATE_DISABLE;\
+       type DPSTREAMCLK3_GATE_DISABLE;\
 
 struct dccg_shift {
        DCCG_REG_FIELD_LIST(uint8_t)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c
index 142efd390d8625a072eacd643f9f74e86384b8a5..f1ba7bb792ea2696719e660a1d1d4f4b62ec8c9e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c
@@ -506,6 +506,64 @@ static void dccg35_dpp_root_clock_control(
        dccg->dpp_clock_gated[dpp_inst] = !clock_on;
 }
 
+static void dccg35_disable_symclk32_se(
+               struct dccg *dccg,
+               int hpo_se_inst)
+{
+       struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+       /* set refclk as the source for symclk32_se */
+       switch (hpo_se_inst) {
+       case 0:
+               REG_UPDATE_2(SYMCLK32_SE_CNTL,
+                               SYMCLK32_SE0_SRC_SEL, 0,
+                               SYMCLK32_SE0_EN, 0);
+               if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) {
+                       REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+                                       SYMCLK32_SE0_GATE_DISABLE, 0);
+//                     REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+//                                     SYMCLK32_ROOT_SE0_GATE_DISABLE, 0);
+               }
+               break;
+       case 1:
+               REG_UPDATE_2(SYMCLK32_SE_CNTL,
+                               SYMCLK32_SE1_SRC_SEL, 0,
+                               SYMCLK32_SE1_EN, 0);
+               if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) {
+                       REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+                                       SYMCLK32_SE1_GATE_DISABLE, 0);
+//                     REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+//                                     SYMCLK32_ROOT_SE1_GATE_DISABLE, 0);
+               }
+               break;
+       case 2:
+               REG_UPDATE_2(SYMCLK32_SE_CNTL,
+                               SYMCLK32_SE2_SRC_SEL, 0,
+                               SYMCLK32_SE2_EN, 0);
+               if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) {
+                       REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+                                       SYMCLK32_SE2_GATE_DISABLE, 0);
+//                     REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+//                                     SYMCLK32_ROOT_SE2_GATE_DISABLE, 0);
+               }
+               break;
+       case 3:
+               REG_UPDATE_2(SYMCLK32_SE_CNTL,
+                               SYMCLK32_SE3_SRC_SEL, 0,
+                               SYMCLK32_SE3_EN, 0);
+               if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) {
+                       REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+                                       SYMCLK32_SE3_GATE_DISABLE, 0);
+//                     REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+//                                     SYMCLK32_ROOT_SE3_GATE_DISABLE, 0);
+               }
+               break;
+       default:
+               BREAK_TO_DEBUGGER();
+               return;
+       }
+}
+
 void dccg35_init(struct dccg *dccg)
 {
        int otg_inst;
@@ -514,7 +572,7 @@ void dccg35_init(struct dccg *dccg)
         * will cause DCN to hang.
         */
        for (otg_inst = 0; otg_inst < 4; otg_inst++)
-               dccg31_disable_symclk32_se(dccg, otg_inst);
+               dccg35_disable_symclk32_se(dccg, otg_inst);
 
        if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)
                for (otg_inst = 0; otg_inst < 2; otg_inst++)
@@ -788,7 +846,7 @@ static const struct dccg_funcs dccg35_funcs = {
        .dccg_init = dccg35_init,
        .set_dpstreamclk = dccg35_set_dpstreamclk,
        .enable_symclk32_se = dccg31_enable_symclk32_se,
-       .disable_symclk32_se = dccg31_disable_symclk32_se,
+       .disable_symclk32_se = dccg35_disable_symclk32_se,
        .enable_symclk32_le = dccg31_enable_symclk32_le,
        .disable_symclk32_le = dccg31_disable_symclk32_le,
        .set_symclk32_le_root_clock_gating = dccg31_set_symclk32_le_root_clock_gating,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.h
index bde48bee0119b7a8c36da6ed9f1196f23ce68ecb..1586a45ca3bd405751a2ea3ee167dc533e67cc96 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.h
@@ -34,6 +34,7 @@
 #define DCCG_REG_LIST_DCN35() \
        DCCG_REG_LIST_DCN314(),\
        SR(DPPCLK_CTRL),\
+       SR(DCCG_GATE_DISABLE_CNTL4),\
        SR(DCCG_GATE_DISABLE_CNTL5),\
        SR(DCCG_GATE_DISABLE_CNTL6),\
        SR(DCCG_GLOBAL_FGCG_REP_CNTL),\
@@ -180,6 +181,56 @@
        DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, mask_sh),\
        DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, mask_sh),\
        DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DSCCLK0_ROOT_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DSCCLK1_ROOT_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DSCCLK2_ROOT_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DSCCLK3_ROOT_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKA_FE_ROOT_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKB_FE_ROOT_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKC_FE_ROOT_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKD_FE_ROOT_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKE_FE_ROOT_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DPPCLK0_ROOT_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DPPCLK1_ROOT_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DPPCLK2_ROOT_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DPPCLK3_ROOT_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL4, HDMICHARCLK0_ROOT_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL6, HDMISTREAMCLK0_ROOT_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKA_ROOT_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKB_ROOT_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKC_ROOT_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKD_ROOT_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKE_ROOT_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE0_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE1_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE2_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE3_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE0_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE1_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE0_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE1_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE2_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE3_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_LE0_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_LE1_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL4, PHYA_REFCLK_ROOT_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL4, PHYB_REFCLK_ROOT_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL4, PHYC_REFCLK_ROOT_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL4, PHYD_REFCLK_ROOT_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL4, PHYE_REFCLK_ROOT_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_ROOT_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_ROOT_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_ROOT_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_ROOT_GATE_DISABLE, mask_sh),\
+       DCCG_SF(HDMISTREAMCLK0_DTO_PARAM, HDMISTREAMCLK0_DTO_PHASE, mask_sh),\
+       DCCG_SF(HDMISTREAMCLK0_DTO_PARAM, HDMISTREAMCLK0_DTO_MODULO, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL, DISPCLK_DCCG_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL3, HDMISTREAMCLK0_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_GATE_DISABLE, mask_sh),\
 
 struct dccg *dccg35_create(
                struct dc_context *ctx,