iommu/mediatek: Just move code position in hw_init

No functional change too, prepare for mt8195 IOMMU support bank functions.
Some global control settings are in bank0 while the other banks have
their bank independent setting. Here only move the global control
settings and the independent registers together.

Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Link: https://lore.kernel.org/r/20220503071427.2285-26-yong.wu@mediatek.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>

diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index de448d056135acb536d824c47f87fa4810a40c5d..ac1681858af8798d5ed86210bb7d8710df389e7f 100644 (file)
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -803,30 +803,6 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
        }
        writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);
 
-       regval = F_L2_MULIT_HIT_EN |
-               F_TABLE_WALK_FAULT_INT_EN |
-               F_PREETCH_FIFO_OVERFLOW_INT_EN |
-               F_MISS_FIFO_OVERFLOW_INT_EN |
-               F_PREFETCH_FIFO_ERR_INT_EN |
-               F_MISS_FIFO_ERR_INT_EN;
-       writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0);
-
-       regval = F_INT_TRANSLATION_FAULT |
-               F_INT_MAIN_MULTI_HIT_FAULT |
-               F_INT_INVALID_PA_FAULT |
-               F_INT_ENTRY_REPLACEMENT_FAULT |
-               F_INT_TLB_MISS_FAULT |
-               F_INT_MISS_TRANSACTION_FIFO_FAULT |
-               F_INT_PRETETCH_TRANSATION_FIFO_FAULT;
-       writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL);
-
-       if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_LEGACY_IVRP_PADDR))
-               regval = (data->protect_base >> 1) | (data->enable_4GB << 31);
-       else
-               regval = lower_32_bits(data->protect_base) |
-                        upper_32_bits(data->protect_base);
-       writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR);
-
        if (data->enable_4GB &&
            MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_VLD_PA_RNG)) {
                /*
@@ -860,6 +836,30 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
        }
        writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL);
 
+       regval = F_L2_MULIT_HIT_EN |
+               F_TABLE_WALK_FAULT_INT_EN |
+               F_PREETCH_FIFO_OVERFLOW_INT_EN |
+               F_MISS_FIFO_OVERFLOW_INT_EN |
+               F_PREFETCH_FIFO_ERR_INT_EN |
+               F_MISS_FIFO_ERR_INT_EN;
+       writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0);
+
+       regval = F_INT_TRANSLATION_FAULT |
+               F_INT_MAIN_MULTI_HIT_FAULT |
+               F_INT_INVALID_PA_FAULT |
+               F_INT_ENTRY_REPLACEMENT_FAULT |
+               F_INT_TLB_MISS_FAULT |
+               F_INT_MISS_TRANSACTION_FIFO_FAULT |
+               F_INT_PRETETCH_TRANSATION_FIFO_FAULT;
+       writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL);
+
+       if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_LEGACY_IVRP_PADDR))
+               regval = (data->protect_base >> 1) | (data->enable_4GB << 31);
+       else
+               regval = lower_32_bits(data->protect_base) |
+                        upper_32_bits(data->protect_base);
+       writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR);
+
        if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,
                             dev_name(data->dev), (void *)data)) {
                writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR);