riscv: dts: starfive: jh7110: Add watchdog node

Add the watchdog node for the Starfive JH7110 SoC.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: Walker Chen <walker.chen@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 30e1f34d5cf8dc63ec05f17707fb9b7e0b39713f..03c6cc49fa229e080aaf731e61276ff95585cdaf 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -469,6 +469,16 @@
                        #gpio-cells = <2>;
                };
 
+               watchdog@13070000 {
+                       compatible = "starfive,jh7110-wdt";
+                       reg = <0x0 0x13070000 0x0 0x10000>;
+                       clocks = <&syscrg JH7110_SYSCLK_WDT_APB>,
+                                <&syscrg JH7110_SYSCLK_WDT_CORE>;
+                       clock-names = "apb", "core";
+                       resets = <&syscrg JH7110_SYSRST_WDT_APB>,
+                                <&syscrg JH7110_SYSRST_WDT_CORE>;
+               };
+
                aoncrg: clock-controller@17000000 {
                        compatible = "starfive,jh7110-aoncrg";
                        reg = <0x0 0x17000000 0x0 0x10000>;