arm64: zynqmp: Use assigned-clock-rates for setting up SD clock in SOM

With limited low level configuration done via psu-init only IPs connected
on SOM are initialized and configured. All IPs connected to carrier card
are not initialized. There is a need to do proper reset, pin configuration
and also clock setting.
The patch targets the last part which is setting up proper clock for EMMC
on production SOMs and SD on kv260-revB.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/cf5a4e412e1674500a71a0b1eed7fa8393f37ae9.1683034376.git.michal.simek@amd.com

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
index 5e7e1bf5b811530d37f85aaf53279b99408805af..681885c9bcbb0a8e6181771e21f35d6abf3ad9f0 100644 (file)
--- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
@@ -2,7 +2,8 @@
 /*
  * Clock specification for Xilinx ZynqMP
  *
- * (C) Copyright 2017 - 2021, Xilinx, Inc.
+ * (C) Copyright 2017 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
  *
  * Michal Simek <michal.simek@xilinx.com>
  */
@@ -185,10 +186,12 @@
 
 &sdhci0 {
        clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;
+       assigned-clocks = <&zynqmp_clk SDIO0_REF>;
 };
 
 &sdhci1 {
        clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;
+       assigned-clocks = <&zynqmp_clk SDIO1_REF>;
 };
 
 &spi0 {

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
index b610e65e0cdfee767fe7a2b5235935bdb9b83dfc..22fe9c4e4d4373c3d96afe1f229acb84efc03a80 100644 (file)
--- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
@@ -132,6 +132,7 @@
        no-1-8-v;
        disable-wp;
        xlnx,mio-bank = <1>;
+       assigned-clock-rates = <187498123>;
 };
 
 &gem3 { /* required by spec */

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
index a52dafbfd59e70e0924a73044c97b04c30945cc2..ca3429f9961ac4f1470e79b4b390dbd1c612ab12 100644 (file)
--- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
@@ -115,6 +115,7 @@
        clk-phase-sd-hs = <126>, <60>;
        clk-phase-uhs-sdr25 = <120>, <60>;
        clk-phase-uhs-ddr50 = <126>, <48>;
+       assigned-clock-rates = <187498123>;
 };
 
 &gem3 { /* required by spec */

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts
index 00c0455635b8b50b27f402e61dc35acd07babc02..d8b2c30caf2c99a2571890b01d030b8f942479ed 100644 (file)
--- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts
@@ -178,6 +178,7 @@
        disable-wp;
        bus-width = <8>;
        xlnx,mio-bank = <0>;
+       assigned-clock-rates = <187498123>;
 };
 
 &spi1 { /* MIO6, 9-11 */