drm/amd/display: Revert Reduce delay when sink device not able to ACK 00340h write

[WHY]
It causes regression AMD source will not write DPCD 340.

Reviewed-by: Wayne Lin <Wayne.Lin@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Ian Chen <ian.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 342e906ae26e41498ef9a3f60c3da21f576c76ad..1ca3328b492c806f7de4b0876433070616229cb2 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1916,12 +1916,6 @@ struct dc_link *link_create(const struct link_init_data *init_params)
        if (false == dc_link_construct(link, init_params))
                goto construct_fail;
 
-       /*
-        * Must use preferred_link_setting, not reported_link_cap or verified_link_cap,
-        * since struct preferred_link_setting won't be reset after S3.
-        */
-       link->preferred_link_setting.dpcd_source_device_specific_field_support = true;
-
        return link;
 
 construct_fail:

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index dedd1246ce5884af51ac87307c65b5fe171cee43..475ad3eed002dec26327ca9e2ea281bcc0ac9b01 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -6554,18 +6554,10 @@ void dpcd_set_source_specific_data(struct dc_link *link)
 
                        uint8_t hblank_size = (uint8_t)link->dc->caps.min_horizontal_blanking_period;
 
-                       if (link->preferred_link_setting.dpcd_source_device_specific_field_support) {
-                               result_write_min_hblank = core_link_write_dpcd(link,
-                                       DP_SOURCE_MINIMUM_HBLANK_SUPPORTED, (uint8_t *)(&hblank_size),
-                                       sizeof(hblank_size));
-
-                               if (result_write_min_hblank == DC_ERROR_UNEXPECTED)
-                                       link->preferred_link_setting.dpcd_source_device_specific_field_support = false;
-                       } else {
-                               DC_LOG_DC("Sink device does not support 00340h DPCD write. Skipping on purpose.\n");
-                       }
+                       result_write_min_hblank = core_link_write_dpcd(link,
+                               DP_SOURCE_MINIMUM_HBLANK_SUPPORTED, (uint8_t *)(&hblank_size),
+                               sizeof(hblank_size));
                }
-
                DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
                                                        WPP_BIT_FLAG_DC_DETECTION_DP_CAPS,
                                                        "result=%u link_index=%u enum dce_version=%d DPCD=0x%04X min_hblank=%u branch_dev_id=0x%x branch_dev_name='%c%c%c%c%c%c'",

diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
index 2c54b6e0498bffaa770f7190bb6868d9b2e96af3..296793d8b2bf25011580e708eb6e5a0d249c0fec 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
@@ -149,7 +149,6 @@ struct dc_link_settings {
        enum dc_link_spread link_spread;
        bool use_link_rate_set;
        uint8_t link_rate_set;
-       bool dpcd_source_device_specific_field_support;
 };
 
 union dc_dp_ffe_preset {