RISC-V: KVM: avoid EBUSY when writing the same machine ID val

Right now we do not allow any write in mvendorid/marchid/mimpid if the
vcpu already started, preventing these regs to be changed.

However, if userspace doesn't change them, an alternative is to consider
the reg write a no-op and avoid erroring out altogether. Userpace can
then be oblivious about KVM internals if no changes were intended in the
first place.

Allow the same form of 'lazy writing' that registers such as
zicbom/zicboz_block_size supports: avoid erroring out if userspace makes
no changes in mvendorid/marchid/mimpid during reg write.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Anup Patel <anup@brainfault.org>

diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c
index a0b0364b038fea335f61c3b930b10fcdbb781859..81cb6b2784db257fef648344238e84fc52c49955 100644 (file)
--- a/arch/riscv/kvm/vcpu_onereg.c
+++ b/arch/riscv/kvm/vcpu_onereg.c
@@ -235,18 +235,24 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu,
                        return -EINVAL;
                break;
        case KVM_REG_RISCV_CONFIG_REG(mvendorid):
+               if (reg_val == vcpu->arch.mvendorid)
+                       break;
                if (!vcpu->arch.ran_atleast_once)
                        vcpu->arch.mvendorid = reg_val;
                else
                        return -EBUSY;
                break;
        case KVM_REG_RISCV_CONFIG_REG(marchid):
+               if (reg_val == vcpu->arch.marchid)
+                       break;
                if (!vcpu->arch.ran_atleast_once)
                        vcpu->arch.marchid = reg_val;
                else
                        return -EBUSY;
                break;
        case KVM_REG_RISCV_CONFIG_REG(mimpid):
+               if (reg_val == vcpu->arch.mimpid)
+                       break;
                if (!vcpu->arch.ran_atleast_once)
                        vcpu->arch.mimpid = reg_val;
                else