drm/amd/display: Pass display_pipe_params_st as const in DML

[ Upstream commit 22667e6ec6b2ce9ca706e9061660b059725d009c ]

[Why]
This neither needs to be on the stack nor passed by value
to each function call. In fact, when building with clang
it seems to break the Linux's default 1024 byte stack
frame limit.

[How]
We can simply pass this as a const pointer.

This patch fixes these Coverity IDs
Addresses-Coverity-ID: 1424031: ("Big parameter passed by value")
Addresses-Coverity-ID: 1423970: ("Big parameter passed by value")
Addresses-Coverity-ID: 1423941: ("Big parameter passed by value")
Addresses-Coverity-ID: 1451742: ("Big parameter passed by value")
Addresses-Coverity-ID: 1451887: ("Big parameter passed by value")
Addresses-Coverity-ID: 1454146: ("Big parameter passed by value")
Addresses-Coverity-ID: 1454152: ("Big parameter passed by value")
Addresses-Coverity-ID: 1454413: ("Big parameter passed by value")
Addresses-Coverity-ID: 1466144: ("Big parameter passed by value")
Addresses-Coverity-ID: 1487237: ("Big parameter passed by value")

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Fixes: 3fe617ccafd6 ("Enable '-Werror' by default for all kernel builds")
Cc: Nick Desaulniers <ndesaulniers@google.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: amd-gfx@lists.freedesktop.org
Cc: Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Cc: Arnd Bergmann <arnd@kernel.org>
Cc: Leo Li <sunpeng.li@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: Xinhui Pan <Xinhui.Pan@amd.com>
Cc: Nathan Chancellor <nathan@kernel.org>
Cc: Guenter Roeck <linux@roeck-us.net>
Cc: llvm@lists.linux.dev
Acked-by: Christian König <christian.koenig@amd.com>
Build-tested-by: Nathan Chancellor <nathan@kernel.org>
Reviewed-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index f2f258e70f9dae16f02752feaa589f614778f45e..34a126816133e082fe0f071804e13fb6d81a42d6 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -3152,7 +3152,7 @@ void dcn20_calculate_dlg_params(
 
                context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml,
                                &context->res_ctx.pipe_ctx[i].rq_regs,
-                               pipes[pipe_idx].pipe);
+                               &pipes[pipe_idx].pipe);
                pipe_idx++;
        }
 }

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
index 2091dd8c252da9734191f25af2ea1f813d6f151e..8c168f348a27f0e090137bff206e59fbf2c64506 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
@@ -768,12 +768,12 @@ static void dml20_rq_dlg_get_rq_params(struct display_mode_lib *mode_lib,
 
 void dml20_rq_dlg_get_rq_reg(struct display_mode_lib *mode_lib,
                display_rq_regs_st *rq_regs,
-               const display_pipe_params_st pipe_param)
+               const display_pipe_params_st *pipe_param)
 {
        display_rq_params_st rq_param = {0};
 
        memset(rq_regs, 0, sizeof(*rq_regs));
-       dml20_rq_dlg_get_rq_params(mode_lib, &rq_param, pipe_param.src);
+       dml20_rq_dlg_get_rq_params(mode_lib, &rq_param, pipe_param->src);
        extract_rq_regs(mode_lib, rq_regs, rq_param);
 
        print__rq_regs_st(mode_lib, *rq_regs);
@@ -1549,7 +1549,7 @@ static void dml20_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib,
 void dml20_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib,
                display_dlg_regs_st *dlg_regs,
                display_ttu_regs_st *ttu_regs,
-               display_e2e_pipe_params_st *e2e_pipe_param,
+               const display_e2e_pipe_params_st *e2e_pipe_param,
                const unsigned int num_pipes,
                const unsigned int pipe_idx,
                const bool cstate_en,

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h
index d0b90947f5409f97518446b5459f999ab93cb6c9..8b23867e97c186ea800fa0160eb83df8dd341b29 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h
@@ -43,7 +43,7 @@ struct display_mode_lib;
 void dml20_rq_dlg_get_rq_reg(
                struct display_mode_lib *mode_lib,
                display_rq_regs_st *rq_regs,
-               const display_pipe_params_st pipe_param);
+               const display_pipe_params_st *pipe_param);
 
 
 // Function: dml_rq_dlg_get_dlg_reg
@@ -61,7 +61,7 @@ void dml20_rq_dlg_get_dlg_reg(
                struct display_mode_lib *mode_lib,
                display_dlg_regs_st *dlg_regs,
                display_ttu_regs_st *ttu_regs,
-               display_e2e_pipe_params_st *e2e_pipe_param,
+               const display_e2e_pipe_params_st *e2e_pipe_param,
                const unsigned int num_pipes,
                const unsigned int pipe_idx,
                const bool cstate_en,

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
index 1a0c14e465faa8f00190728d9980a03120a27620..26ececfd40cdca5afa53d1814f08234fbc69171e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
@@ -768,12 +768,12 @@ static void dml20v2_rq_dlg_get_rq_params(struct display_mode_lib *mode_lib,
 
 void dml20v2_rq_dlg_get_rq_reg(struct display_mode_lib *mode_lib,
                display_rq_regs_st *rq_regs,
-               const display_pipe_params_st pipe_param)
+               const display_pipe_params_st *pipe_param)
 {
        display_rq_params_st rq_param = {0};
 
        memset(rq_regs, 0, sizeof(*rq_regs));
-       dml20v2_rq_dlg_get_rq_params(mode_lib, &rq_param, pipe_param.src);
+       dml20v2_rq_dlg_get_rq_params(mode_lib, &rq_param, pipe_param->src);
        extract_rq_regs(mode_lib, rq_regs, rq_param);
 
        print__rq_regs_st(mode_lib, *rq_regs);
@@ -1550,7 +1550,7 @@ static void dml20v2_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib,
 void dml20v2_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib,
                display_dlg_regs_st *dlg_regs,
                display_ttu_regs_st *ttu_regs,
-               display_e2e_pipe_params_st *e2e_pipe_param,
+               const display_e2e_pipe_params_st *e2e_pipe_param,
                const unsigned int num_pipes,
                const unsigned int pipe_idx,
                const bool cstate_en,

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h
index 27cf8bed9376fc3cc252c85af9f56727aaae406f..2b4e46ea1c3df3af03c3ed3c047688709080be1e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h
@@ -43,7 +43,7 @@ struct display_mode_lib;
 void dml20v2_rq_dlg_get_rq_reg(
                struct display_mode_lib *mode_lib,
                display_rq_regs_st *rq_regs,
-               const display_pipe_params_st pipe_param);
+               const display_pipe_params_st *pipe_param);
 
 
 // Function: dml_rq_dlg_get_dlg_reg
@@ -61,7 +61,7 @@ void dml20v2_rq_dlg_get_dlg_reg(
                struct display_mode_lib *mode_lib,
                display_dlg_regs_st *dlg_regs,
                display_ttu_regs_st *ttu_regs,
-               display_e2e_pipe_params_st *e2e_pipe_param,
+               const display_e2e_pipe_params_st *e2e_pipe_param,
                const unsigned int num_pipes,
                const unsigned int pipe_idx,
                const bool cstate_en,

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
index 287e31052b3079a9520ccd7034f126647f39a6fe..736978c4d40a123395e6d37d0946281ed635f10c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
@@ -694,7 +694,7 @@ static void get_surf_rq_param(
                display_data_rq_sizing_params_st *rq_sizing_param,
                display_data_rq_dlg_params_st *rq_dlg_param,
                display_data_rq_misc_params_st *rq_misc_param,
-               const display_pipe_params_st pipe_param,
+               const display_pipe_params_st *pipe_param,
                bool is_chroma)
 {
        bool mode_422 = false;
@@ -706,30 +706,30 @@ static void get_surf_rq_param(
 
        // FIXME check if ppe apply for both luma and chroma in 422 case
        if (is_chroma) {
-               vp_width = pipe_param.src.viewport_width_c / ppe;
-               vp_height = pipe_param.src.viewport_height_c;
-               data_pitch = pipe_param.src.data_pitch_c;
-               meta_pitch = pipe_param.src.meta_pitch_c;
+               vp_width = pipe_param->src.viewport_width_c / ppe;
+               vp_height = pipe_param->src.viewport_height_c;
+               data_pitch = pipe_param->src.data_pitch_c;
+               meta_pitch = pipe_param->src.meta_pitch_c;
        } else {
-               vp_width = pipe_param.src.viewport_width / ppe;
-               vp_height = pipe_param.src.viewport_height;
-               data_pitch = pipe_param.src.data_pitch;
-               meta_pitch = pipe_param.src.meta_pitch;
+               vp_width = pipe_param->src.viewport_width / ppe;
+               vp_height = pipe_param->src.viewport_height;
+               data_pitch = pipe_param->src.data_pitch;
+               meta_pitch = pipe_param->src.meta_pitch;
        }
 
-       if (pipe_param.dest.odm_combine) {
+       if (pipe_param->dest.odm_combine) {
                unsigned int access_dir;
                unsigned int full_src_vp_width;
                unsigned int hactive_half;
                unsigned int src_hactive_half;
-               access_dir = (pipe_param.src.source_scan == dm_vert); // vp access direction: horizontal or vertical accessed
-               hactive_half  = pipe_param.dest.hactive / 2;
+               access_dir = (pipe_param->src.source_scan == dm_vert); // vp access direction: horizontal or vertical accessed
+               hactive_half  = pipe_param->dest.hactive / 2;
                if (is_chroma) {
-                       full_src_vp_width = pipe_param.scale_ratio_depth.hscl_ratio_c * pipe_param.dest.full_recout_width;
-                       src_hactive_half  = pipe_param.scale_ratio_depth.hscl_ratio_c * hactive_half;
+                       full_src_vp_width = pipe_param->scale_ratio_depth.hscl_ratio_c * pipe_param->dest.full_recout_width;
+                       src_hactive_half  = pipe_param->scale_ratio_depth.hscl_ratio_c * hactive_half;
                } else {
-                       full_src_vp_width = pipe_param.scale_ratio_depth.hscl_ratio * pipe_param.dest.full_recout_width;
-                       src_hactive_half  = pipe_param.scale_ratio_depth.hscl_ratio * hactive_half;
+                       full_src_vp_width = pipe_param->scale_ratio_depth.hscl_ratio * pipe_param->dest.full_recout_width;
+                       src_hactive_half  = pipe_param->scale_ratio_depth.hscl_ratio * hactive_half;
                }
 
                if (access_dir == 0) {
@@ -754,7 +754,7 @@ static void get_surf_rq_param(
        rq_sizing_param->meta_chunk_bytes = 2048;
        rq_sizing_param->min_meta_chunk_bytes = 256;
 
-       if (pipe_param.src.hostvm)
+       if (pipe_param->src.hostvm)
                rq_sizing_param->mpte_group_bytes = 512;
        else
                rq_sizing_param->mpte_group_bytes = 2048;
@@ -768,23 +768,23 @@ static void get_surf_rq_param(
                        vp_height,
                        data_pitch,
                        meta_pitch,
-                       pipe_param.src.source_format,
-                       pipe_param.src.sw_mode,
-                       pipe_param.src.macro_tile_size,
-                       pipe_param.src.source_scan,
-                       pipe_param.src.hostvm,
+                       pipe_param->src.source_format,
+                       pipe_param->src.sw_mode,
+                       pipe_param->src.macro_tile_size,
+                       pipe_param->src.source_scan,
+                       pipe_param->src.hostvm,
                        is_chroma);
 }
 
 static void dml_rq_dlg_get_rq_params(
                struct display_mode_lib *mode_lib,
                display_rq_params_st *rq_param,
-               const display_pipe_params_st pipe_param)
+               const display_pipe_params_st *pipe_param)
 {
        // get param for luma surface
-       rq_param->yuv420 = pipe_param.src.source_format == dm_420_8
-                       || pipe_param.src.source_format == dm_420_10;
-       rq_param->yuv420_10bpc = pipe_param.src.source_format == dm_420_10;
+       rq_param->yuv420 = pipe_param->src.source_format == dm_420_8
+                       || pipe_param->src.source_format == dm_420_10;
+       rq_param->yuv420_10bpc = pipe_param->src.source_format == dm_420_10;
 
        get_surf_rq_param(
                        mode_lib,
@@ -794,7 +794,7 @@ static void dml_rq_dlg_get_rq_params(
                        pipe_param,
                        0);
 
-       if (is_dual_plane((enum source_format_class) (pipe_param.src.source_format))) {
+       if (is_dual_plane((enum source_format_class) (pipe_param->src.source_format))) {
                // get param for chroma surface
                get_surf_rq_param(
                                mode_lib,
@@ -806,14 +806,14 @@ static void dml_rq_dlg_get_rq_params(
        }
 
        // calculate how to split the det buffer space between luma and chroma
-       handle_det_buf_split(mode_lib, rq_param, pipe_param.src);
+       handle_det_buf_split(mode_lib, rq_param, pipe_param->src);
        print__rq_params_st(mode_lib, *rq_param);
 }
 
 void dml21_rq_dlg_get_rq_reg(
                struct display_mode_lib *mode_lib,
                display_rq_regs_st *rq_regs,
-               const display_pipe_params_st pipe_param)
+               const display_pipe_params_st *pipe_param)
 {
        display_rq_params_st rq_param = {0};
 
@@ -1658,7 +1658,7 @@ void dml21_rq_dlg_get_dlg_reg(
                struct display_mode_lib *mode_lib,
                display_dlg_regs_st *dlg_regs,
                display_ttu_regs_st *ttu_regs,
-               display_e2e_pipe_params_st *e2e_pipe_param,
+               const display_e2e_pipe_params_st *e2e_pipe_param,
                const unsigned int num_pipes,
                const unsigned int pipe_idx,
                const bool cstate_en,
@@ -1696,7 +1696,7 @@ void dml21_rq_dlg_get_dlg_reg(
        // system parameter calculation done
 
        dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx);
-       dml_rq_dlg_get_rq_params(mode_lib, &rq_param, e2e_pipe_param[pipe_idx].pipe);
+       dml_rq_dlg_get_rq_params(mode_lib, &rq_param, &e2e_pipe_param[pipe_idx].pipe);
        dml_rq_dlg_get_dlg_params(
                        mode_lib,
                        e2e_pipe_param,

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.h b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.h
index e8f7785e3fc639188dd78224846811f029d1fca4..af6ad0ca9cf8a542e3040570f61e9803944ff29d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.h
@@ -44,7 +44,7 @@ struct display_mode_lib;
 void dml21_rq_dlg_get_rq_reg(
                struct display_mode_lib *mode_lib,
                display_rq_regs_st *rq_regs,
-               const display_pipe_params_st pipe_param);
+               const display_pipe_params_st *pipe_param);
 
 // Function: dml_rq_dlg_get_dlg_reg
 //   Calculate and return DLG and TTU register struct given the system setting
@@ -61,7 +61,7 @@ void dml21_rq_dlg_get_dlg_reg(
                struct display_mode_lib *mode_lib,
                display_dlg_regs_st *dlg_regs,
                display_ttu_regs_st *ttu_regs,
-               display_e2e_pipe_params_st *e2e_pipe_param,
+               const display_e2e_pipe_params_st *e2e_pipe_param,
                const unsigned int num_pipes,
                const unsigned int pipe_idx,
                const bool cstate_en,

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
index 0d934fae1c3a60b603cd7384089fe963ebd718d1..2120e0941a095a85cb77ce7c816e45c6c494a795 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
@@ -747,7 +747,7 @@ static void get_surf_rq_param(struct display_mode_lib *mode_lib,
        display_data_rq_sizing_params_st *rq_sizing_param,
        display_data_rq_dlg_params_st *rq_dlg_param,
        display_data_rq_misc_params_st *rq_misc_param,
-       const display_pipe_params_st pipe_param,
+       const display_pipe_params_st *pipe_param,
        bool is_chroma,
        bool is_alpha)
 {
@@ -761,32 +761,32 @@ static void get_surf_rq_param(struct display_mode_lib *mode_lib,
 
        // FIXME check if ppe apply for both luma and chroma in 422 case
        if (is_chroma | is_alpha) {
-               vp_width = pipe_param.src.viewport_width_c / ppe;
-               vp_height = pipe_param.src.viewport_height_c;
-               data_pitch = pipe_param.src.data_pitch_c;
-               meta_pitch = pipe_param.src.meta_pitch_c;
-               surface_height = pipe_param.src.surface_height_y / 2.0;
+               vp_width = pipe_param->src.viewport_width_c / ppe;
+               vp_height = pipe_param->src.viewport_height_c;
+               data_pitch = pipe_param->src.data_pitch_c;
+               meta_pitch = pipe_param->src.meta_pitch_c;
+               surface_height = pipe_param->src.surface_height_y / 2.0;
        } else {
-               vp_width = pipe_param.src.viewport_width / ppe;
-               vp_height = pipe_param.src.viewport_height;
-               data_pitch = pipe_param.src.data_pitch;
-               meta_pitch = pipe_param.src.meta_pitch;
-               surface_height = pipe_param.src.surface_height_y;
+               vp_width = pipe_param->src.viewport_width / ppe;
+               vp_height = pipe_param->src.viewport_height;
+               data_pitch = pipe_param->src.data_pitch;
+               meta_pitch = pipe_param->src.meta_pitch;
+               surface_height = pipe_param->src.surface_height_y;
        }
 
-       if (pipe_param.dest.odm_combine) {
+       if (pipe_param->dest.odm_combine) {
                unsigned int access_dir = 0;
                unsigned int full_src_vp_width = 0;
                unsigned int hactive_odm = 0;
                unsigned int src_hactive_odm = 0;
-               access_dir = (pipe_param.src.source_scan == dm_vert); // vp access direction: horizontal or vertical accessed
-               hactive_odm  = pipe_param.dest.hactive / ((unsigned int)pipe_param.dest.odm_combine*2);
+               access_dir = (pipe_param->src.source_scan == dm_vert); // vp access direction: horizontal or vertical accessed
+               hactive_odm  = pipe_param->dest.hactive / ((unsigned int) pipe_param->dest.odm_combine*2);
                if (is_chroma) {
-                       full_src_vp_width = pipe_param.scale_ratio_depth.hscl_ratio_c * pipe_param.dest.full_recout_width;
-                       src_hactive_odm  = pipe_param.scale_ratio_depth.hscl_ratio_c * hactive_odm;
+                       full_src_vp_width = pipe_param->scale_ratio_depth.hscl_ratio_c * pipe_param->dest.full_recout_width;
+                       src_hactive_odm  = pipe_param->scale_ratio_depth.hscl_ratio_c * hactive_odm;
                } else {
-                       full_src_vp_width = pipe_param.scale_ratio_depth.hscl_ratio * pipe_param.dest.full_recout_width;
-                       src_hactive_odm  = pipe_param.scale_ratio_depth.hscl_ratio * hactive_odm;
+                       full_src_vp_width = pipe_param->scale_ratio_depth.hscl_ratio * pipe_param->dest.full_recout_width;
+                       src_hactive_odm  = pipe_param->scale_ratio_depth.hscl_ratio * hactive_odm;
                }
 
                if (access_dir == 0) {
@@ -815,7 +815,7 @@ static void get_surf_rq_param(struct display_mode_lib *mode_lib,
        rq_sizing_param->meta_chunk_bytes = 2048;
        rq_sizing_param->min_meta_chunk_bytes = 256;
 
-       if (pipe_param.src.hostvm)
+       if (pipe_param->src.hostvm)
                rq_sizing_param->mpte_group_bytes = 512;
        else
                rq_sizing_param->mpte_group_bytes = 2048;
@@ -828,28 +828,28 @@ static void get_surf_rq_param(struct display_mode_lib *mode_lib,
                vp_height,
                data_pitch,
                meta_pitch,
-               pipe_param.src.source_format,
-               pipe_param.src.sw_mode,
-               pipe_param.src.macro_tile_size,
-               pipe_param.src.source_scan,
-               pipe_param.src.hostvm,
+               pipe_param->src.source_format,
+               pipe_param->src.sw_mode,
+               pipe_param->src.macro_tile_size,
+               pipe_param->src.source_scan,
+               pipe_param->src.hostvm,
                is_chroma,
                surface_height);
 }
 
 static void dml_rq_dlg_get_rq_params(struct display_mode_lib *mode_lib,
        display_rq_params_st *rq_param,
-       const display_pipe_params_st pipe_param)
+       const display_pipe_params_st *pipe_param)
 {
        // get param for luma surface
-       rq_param->yuv420 = pipe_param.src.source_format == dm_420_8
-       || pipe_param.src.source_format == dm_420_10
-       || pipe_param.src.source_format == dm_rgbe_alpha
-       || pipe_param.src.source_format == dm_420_12;
+       rq_param->yuv420 = pipe_param->src.source_format == dm_420_8
+       || pipe_param->src.source_format == dm_420_10
+       || pipe_param->src.source_format == dm_rgbe_alpha
+       || pipe_param->src.source_format == dm_420_12;
 
-       rq_param->yuv420_10bpc = pipe_param.src.source_format == dm_420_10;
+       rq_param->yuv420_10bpc = pipe_param->src.source_format == dm_420_10;
 
-       rq_param->rgbe_alpha = (pipe_param.src.source_format == dm_rgbe_alpha)?1:0;
+       rq_param->rgbe_alpha = (pipe_param->src.source_format == dm_rgbe_alpha)?1:0;
 
        get_surf_rq_param(mode_lib,
                &(rq_param->sizing.rq_l),
@@ -859,7 +859,7 @@ static void dml_rq_dlg_get_rq_params(struct display_mode_lib *mode_lib,
                0,
                0);
 
-       if (is_dual_plane((enum source_format_class)(pipe_param.src.source_format))) {
+       if (is_dual_plane((enum source_format_class)(pipe_param->src.source_format))) {
                // get param for chroma surface
                get_surf_rq_param(mode_lib,
                        &(rq_param->sizing.rq_c),
@@ -871,13 +871,13 @@ static void dml_rq_dlg_get_rq_params(struct display_mode_lib *mode_lib,
        }
 
        // calculate how to split the det buffer space between luma and chroma
-       handle_det_buf_split(mode_lib, rq_param, pipe_param.src);
+       handle_det_buf_split(mode_lib, rq_param, pipe_param->src);
        print__rq_params_st(mode_lib, *rq_param);
 }
 
 void dml30_rq_dlg_get_rq_reg(struct display_mode_lib *mode_lib,
        display_rq_regs_st *rq_regs,
-       const display_pipe_params_st pipe_param)
+       const display_pipe_params_st *pipe_param)
 {
        display_rq_params_st rq_param = { 0 };
 
@@ -1831,7 +1831,7 @@ static void dml_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib,
 void dml30_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib,
        display_dlg_regs_st *dlg_regs,
        display_ttu_regs_st *ttu_regs,
-       display_e2e_pipe_params_st *e2e_pipe_param,
+       const display_e2e_pipe_params_st *e2e_pipe_param,
        const unsigned int num_pipes,
        const unsigned int pipe_idx,
        const bool cstate_en,
@@ -1866,7 +1866,7 @@ void dml30_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib,
        // system parameter calculation done
 
        dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx);
-       dml_rq_dlg_get_rq_params(mode_lib, &rq_param, e2e_pipe_param[pipe_idx].pipe);
+       dml_rq_dlg_get_rq_params(mode_lib, &rq_param, &e2e_pipe_param[pipe_idx].pipe);
        dml_rq_dlg_get_dlg_params(mode_lib,
                e2e_pipe_param,
                num_pipes,

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.h b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.h
index c04965cceff35aec2e11154f647674c608291c70..625e41f8d57512859376acc2b76981f7fd27c0cd 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.h
@@ -41,7 +41,7 @@ struct display_mode_lib;
 //            See also: <display_rq_regs_st>
 void dml30_rq_dlg_get_rq_reg(struct display_mode_lib *mode_lib,
                display_rq_regs_st *rq_regs,
-               const display_pipe_params_st pipe_param);
+               const display_pipe_params_st *pipe_param);
 
 // Function: dml_rq_dlg_get_dlg_reg
 //   Calculate and return DLG and TTU register struct given the system setting
@@ -57,7 +57,7 @@ void dml30_rq_dlg_get_rq_reg(struct display_mode_lib *mode_lib,
 void dml30_rq_dlg_get_dlg_reg(struct display_mode_lib             *mode_lib,
                display_dlg_regs_st          *dlg_regs,
                display_ttu_regs_st          *ttu_regs,
-               display_e2e_pipe_params_st   *e2e_pipe_param,
+               const display_e2e_pipe_params_st   *e2e_pipe_param,
                const unsigned int            num_pipes,
                const unsigned int            pipe_idx,
                const bool                    cstate_en,

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
index c23905bc733ae60af9a706f3c10f75b7c8c5b1c9..57bd4e3f8a823ee7a64739e44dea5b9525c2f2c1 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
@@ -738,7 +738,7 @@ static void get_surf_rq_param(
                display_data_rq_sizing_params_st *rq_sizing_param,
                display_data_rq_dlg_params_st *rq_dlg_param,
                display_data_rq_misc_params_st *rq_misc_param,
-               const display_pipe_params_st pipe_param,
+               const display_pipe_params_st *pipe_param,
                bool is_chroma,
                bool is_alpha)
 {
@@ -752,33 +752,33 @@ static void get_surf_rq_param(
 
        // FIXME check if ppe apply for both luma and chroma in 422 case
        if (is_chroma | is_alpha) {
-               vp_width = pipe_param.src.viewport_width_c / ppe;
-               vp_height = pipe_param.src.viewport_height_c;
-               data_pitch = pipe_param.src.data_pitch_c;
-               meta_pitch = pipe_param.src.meta_pitch_c;
-               surface_height = pipe_param.src.surface_height_y / 2.0;
+               vp_width = pipe_param->src.viewport_width_c / ppe;
+               vp_height = pipe_param->src.viewport_height_c;
+               data_pitch = pipe_param->src.data_pitch_c;
+               meta_pitch = pipe_param->src.meta_pitch_c;
+               surface_height = pipe_param->src.surface_height_y / 2.0;
        } else {
-               vp_width = pipe_param.src.viewport_width / ppe;
-               vp_height = pipe_param.src.viewport_height;
-               data_pitch = pipe_param.src.data_pitch;
-               meta_pitch = pipe_param.src.meta_pitch;
-               surface_height = pipe_param.src.surface_height_y;
+               vp_width = pipe_param->src.viewport_width / ppe;
+               vp_height = pipe_param->src.viewport_height;
+               data_pitch = pipe_param->src.data_pitch;
+               meta_pitch = pipe_param->src.meta_pitch;
+               surface_height = pipe_param->src.surface_height_y;
        }
 
-       if (pipe_param.dest.odm_combine) {
+       if (pipe_param->dest.odm_combine) {
                unsigned int access_dir;
                unsigned int full_src_vp_width;
                unsigned int hactive_odm;
                unsigned int src_hactive_odm;
 
-               access_dir = (pipe_param.src.source_scan == dm_vert); // vp access direction: horizontal or vertical accessed
-               hactive_odm = pipe_param.dest.hactive / ((unsigned int) pipe_param.dest.odm_combine * 2);
+               access_dir = (pipe_param->src.source_scan == dm_vert); // vp access direction: horizontal or vertical accessed
+               hactive_odm = pipe_param->dest.hactive / ((unsigned int) pipe_param->dest.odm_combine * 2);
                if (is_chroma) {
-                       full_src_vp_width = pipe_param.scale_ratio_depth.hscl_ratio_c * pipe_param.dest.full_recout_width;
-                       src_hactive_odm = pipe_param.scale_ratio_depth.hscl_ratio_c * hactive_odm;
+                       full_src_vp_width = pipe_param->scale_ratio_depth.hscl_ratio_c * pipe_param->dest.full_recout_width;
+                       src_hactive_odm = pipe_param->scale_ratio_depth.hscl_ratio_c * hactive_odm;
                } else {
-                       full_src_vp_width = pipe_param.scale_ratio_depth.hscl_ratio * pipe_param.dest.full_recout_width;
-                       src_hactive_odm = pipe_param.scale_ratio_depth.hscl_ratio * hactive_odm;
+                       full_src_vp_width = pipe_param->scale_ratio_depth.hscl_ratio * pipe_param->dest.full_recout_width;
+                       src_hactive_odm = pipe_param->scale_ratio_depth.hscl_ratio * hactive_odm;
                }
 
                if (access_dir == 0) {
@@ -808,7 +808,7 @@ static void get_surf_rq_param(
        rq_sizing_param->meta_chunk_bytes = 2048;
        rq_sizing_param->min_meta_chunk_bytes = 256;
 
-       if (pipe_param.src.hostvm)
+       if (pipe_param->src.hostvm)
                rq_sizing_param->mpte_group_bytes = 512;
        else
                rq_sizing_param->mpte_group_bytes = 2048;
@@ -822,38 +822,38 @@ static void get_surf_rq_param(
                        vp_height,
                        data_pitch,
                        meta_pitch,
-                       pipe_param.src.source_format,
-                       pipe_param.src.sw_mode,
-                       pipe_param.src.macro_tile_size,
-                       pipe_param.src.source_scan,
-                       pipe_param.src.hostvm,
+                       pipe_param->src.source_format,
+                       pipe_param->src.sw_mode,
+                       pipe_param->src.macro_tile_size,
+                       pipe_param->src.source_scan,
+                       pipe_param->src.hostvm,
                        is_chroma,
                        surface_height);
 }
 
-static void dml_rq_dlg_get_rq_params(struct display_mode_lib *mode_lib, display_rq_params_st *rq_param, const display_pipe_params_st pipe_param)
+static void dml_rq_dlg_get_rq_params(struct display_mode_lib *mode_lib, display_rq_params_st *rq_param, const display_pipe_params_st *pipe_param)
 {
        // get param for luma surface
-       rq_param->yuv420 = pipe_param.src.source_format == dm_420_8 || pipe_param.src.source_format == dm_420_10 || pipe_param.src.source_format == dm_rgbe_alpha
-                       || pipe_param.src.source_format == dm_420_12;
+       rq_param->yuv420 = pipe_param->src.source_format == dm_420_8 || pipe_param->src.source_format == dm_420_10 || pipe_param->src.source_format == dm_rgbe_alpha
+                       || pipe_param->src.source_format == dm_420_12;
 
-       rq_param->yuv420_10bpc = pipe_param.src.source_format == dm_420_10;
+       rq_param->yuv420_10bpc = pipe_param->src.source_format == dm_420_10;
 
-       rq_param->rgbe_alpha = (pipe_param.src.source_format == dm_rgbe_alpha) ? 1 : 0;
+       rq_param->rgbe_alpha = (pipe_param->src.source_format == dm_rgbe_alpha) ? 1 : 0;
 
        get_surf_rq_param(mode_lib, &(rq_param->sizing.rq_l), &(rq_param->dlg.rq_l), &(rq_param->misc.rq_l), pipe_param, 0, 0);
 
-       if (is_dual_plane((enum source_format_class) (pipe_param.src.source_format))) {
+       if (is_dual_plane((enum source_format_class) (pipe_param->src.source_format))) {
                // get param for chroma surface
                get_surf_rq_param(mode_lib, &(rq_param->sizing.rq_c), &(rq_param->dlg.rq_c), &(rq_param->misc.rq_c), pipe_param, 1, rq_param->rgbe_alpha);
        }
 
        // calculate how to split the det buffer space between luma and chroma
-       handle_det_buf_split(mode_lib, rq_param, pipe_param.src);
+       handle_det_buf_split(mode_lib, rq_param, pipe_param->src);
        print__rq_params_st(mode_lib, *rq_param);
 }
 
-void dml31_rq_dlg_get_rq_reg(struct display_mode_lib *mode_lib, display_rq_regs_st *rq_regs, const display_pipe_params_st pipe_param)
+void dml31_rq_dlg_get_rq_reg(struct display_mode_lib *mode_lib, display_rq_regs_st *rq_regs, const display_pipe_params_st *pipe_param)
 {
        display_rq_params_st rq_param = {0};
 
@@ -1677,7 +1677,7 @@ void dml31_rq_dlg_get_dlg_reg(
                struct display_mode_lib *mode_lib,
                display_dlg_regs_st *dlg_regs,
                display_ttu_regs_st *ttu_regs,
-               display_e2e_pipe_params_st *e2e_pipe_param,
+               const display_e2e_pipe_params_st *e2e_pipe_param,
                const unsigned int num_pipes,
                const unsigned int pipe_idx,
                const bool cstate_en,
@@ -1704,7 +1704,7 @@ void dml31_rq_dlg_get_dlg_reg(
        // system parameter calculation done
 
        dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx);
-       dml_rq_dlg_get_rq_params(mode_lib, &rq_param, e2e_pipe_param[pipe_idx].pipe);
+       dml_rq_dlg_get_rq_params(mode_lib, &rq_param, &e2e_pipe_param[pipe_idx].pipe);
        dml_rq_dlg_get_dlg_params(
                        mode_lib,
                        e2e_pipe_param,

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.h b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.h
index adf8518f761f9c0e769bf5b83b40a3b614ab968e..8ee991351699dba093457fab666174bea33c3abc 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.h
@@ -41,7 +41,7 @@ struct display_mode_lib;
 //            See also: <display_rq_regs_st>
 void dml31_rq_dlg_get_rq_reg(struct display_mode_lib *mode_lib,
                display_rq_regs_st *rq_regs,
-               const display_pipe_params_st pipe_param);
+               const display_pipe_params_st *pipe_param);
 
 // Function: dml_rq_dlg_get_dlg_reg
 //   Calculate and return DLG and TTU register struct given the system setting
@@ -57,7 +57,7 @@ void dml31_rq_dlg_get_rq_reg(struct display_mode_lib *mode_lib,
 void dml31_rq_dlg_get_dlg_reg(struct display_mode_lib             *mode_lib,
                display_dlg_regs_st          *dlg_regs,
                display_ttu_regs_st          *ttu_regs,
-               display_e2e_pipe_params_st   *e2e_pipe_param,
+               const display_e2e_pipe_params_st *e2e_pipe_param,
                const unsigned int            num_pipes,
                const unsigned int            pipe_idx,
                const bool                    cstate_en,

diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
index d42a0aeca6be2948363f5912b258463e4c0fcfde..72b1957022aa202e7bff82ee8d7e4efeaa78846b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
@@ -49,7 +49,7 @@ struct dml_funcs {
                        struct display_mode_lib *mode_lib,
                        display_dlg_regs_st *dlg_regs,
                        display_ttu_regs_st *ttu_regs,
-                       display_e2e_pipe_params_st *e2e_pipe_param,
+                       const display_e2e_pipe_params_st *e2e_pipe_param,
                        const unsigned int num_pipes,
                        const unsigned int pipe_idx,
                        const bool cstate_en,
@@ -60,7 +60,7 @@ struct dml_funcs {
        void (*rq_dlg_get_rq_reg)(
                struct display_mode_lib *mode_lib,
                display_rq_regs_st *rq_regs,
-               const display_pipe_params_st pipe_param);
+               const display_pipe_params_st *pipe_param);
        void (*recalculate)(struct display_mode_lib *mode_lib);
        void (*validate)(struct display_mode_lib *mode_lib);
 };