drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.

Small changes to intel_dp_mode_valid(), allow listing modes that
can only be supported in the bigjoiner configuration, which is
not supported yet.

v13:
* Allow bigjoiner if hdisplay >5120
v12:
* slice_count logic simplify (Ville)
* Fix unnecessary changes in downstream_mode_valid (Ville)
v11:
* Make intel_dp_can_bigjoiner non static
so it can be used in intel_display (Manasi)
v10:
* Simplify logic (Ville)
* Allow bigjoiner on edp (Ville)
v9:
* Restric Bigjoiner on PORT A (Ville)
v8:
* use source dotclock for max dotclock (Manasi)
v7:
* Add can_bigjoiner() helper (Ville)
* Pass bigjoiner to plane_size validation (Ville)
v6:
* Rebase after dp_downstream mode valid changes (Manasi)
v5:
* Increase max plane width to support 8K with bigjoiner (Maarten)
v4:
* Rebase (Manasi)

Changes since v1:
- Disallow bigjoiner on eDP.
Changes since v2:
- Rename intel_dp_downstream_max_dotclock to intel_dp_max_dotclock,
  and split off the downstream and source checking to its own function.
  (Ville)
v3:
* Rebase (Manasi)

Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
[vsyrjala:
* Keep bigjoiner disabled until everything is ready
* Appease checkpatch]
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201117194718.11462-3-manasi.d.navare@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a1b975ab3bb0ea7e5ab59ac9e1f01efacebe6aee..16c55d8fe4dc54e084a55543e1fbd039cbabed66 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -17780,7 +17780,8 @@ intel_mode_valid(struct drm_device *dev,
 
 enum drm_mode_status
 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
-                               const struct drm_display_mode *mode)
+                               const struct drm_display_mode *mode,
+                               bool bigjoiner)
 {
        int plane_width_max, plane_height_max;
 
@@ -17797,7 +17798,7 @@ intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
         * too big for that.
         */
        if (INTEL_GEN(dev_priv) >= 11) {
-               plane_width_max = 5120;
+               plane_width_max = 5120 << bigjoiner;
                plane_height_max = 4320;
        } else {
                plane_width_max = 5120;

diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 6be14e8571aa7c351bc720ab23a6fd01e505339d..5e0d42d82c110aa27ed8ce981e9defee16cf6708 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -513,7 +513,8 @@ u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
 bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
 enum drm_mode_status
 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
-                               const struct drm_display_mode *mode);
+                               const struct drm_display_mode *mode,
+                               bool bigjoiner);
 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
 bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
 

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index ec8359f03aaf0d4ccf9dd2341d6396d1dd88e440..5ad59610eb120d1909fb2dc9c778e616a7e909cd 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -254,6 +254,20 @@ intel_dp_max_data_rate(int max_link_clock, int max_lanes)
        return max_link_clock * max_lanes;
 }
 
+bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
+{
+       struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+       struct intel_encoder *encoder = &intel_dig_port->base;
+       struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
+       /* FIXME remove once everything is in place */
+       return false;
+
+       return INTEL_GEN(dev_priv) >= 12 ||
+               (INTEL_GEN(dev_priv) == 11 &&
+                encoder->port != PORT_A);
+}
+
 static int cnl_max_source_rate(struct intel_dp *intel_dp)
 {
        struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
@@ -519,7 +533,8 @@ small_joiner_ram_size_bits(struct drm_i915_private *i915)
 
 static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
                                       u32 link_clock, u32 lane_count,
-                                      u32 mode_clock, u32 mode_hdisplay)
+                                      u32 mode_clock, u32 mode_hdisplay,
+                                      bool bigjoiner)
 {
        u32 bits_per_pixel, max_bpp_small_joiner_ram;
        int i;
@@ -537,6 +552,10 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
        /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
        max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
                mode_hdisplay;
+
+       if (bigjoiner)
+               max_bpp_small_joiner_ram *= 2;
+
        drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n",
                    max_bpp_small_joiner_ram);
 
@@ -546,6 +565,15 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
         */
        bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
 
+       if (bigjoiner) {
+               u32 max_bpp_bigjoiner =
+                       i915->max_cdclk_freq * 48 /
+                       intel_dp_mode_to_fec_clock(mode_clock);
+
+               DRM_DEBUG_KMS("Max big joiner bpp: %u\n", max_bpp_bigjoiner);
+               bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
+       }
+
        /* Error out if the max bpp is less than smallest allowed valid bpp */
        if (bits_per_pixel < valid_dsc_bpp[0]) {
                drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
@@ -568,7 +596,8 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
 }
 
 static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
-                                      int mode_clock, int mode_hdisplay)
+                                      int mode_clock, int mode_hdisplay,
+                                      bool bigjoiner)
 {
        struct drm_i915_private *i915 = dp_to_i915(intel_dp);
        u8 min_slice_count, i;
@@ -595,12 +624,18 @@ static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
 
        /* Find the closest match to the valid slice count values */
        for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
-               if (valid_dsc_slicecount[i] >
-                   drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
-                                                   false))
+               u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner;
+
+               if (test_slice_count >
+                   drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false))
                        break;
-               if (min_slice_count  <= valid_dsc_slicecount[i])
-                       return valid_dsc_slicecount[i];
+
+               /* big joiner needs small joiner to be enabled */
+               if (bigjoiner && test_slice_count < 4)
+                       continue;
+
+               if (min_slice_count <= test_slice_count)
+                       return test_slice_count;
        }
 
        drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
@@ -717,6 +752,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
        u16 dsc_max_output_bpp = 0;
        u8 dsc_slice_count = 0;
        enum drm_mode_status status;
+       bool dsc = false, bigjoiner = false;
 
        if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
                return MODE_NO_DBLESCAN;
@@ -737,6 +773,14 @@ intel_dp_mode_valid(struct drm_connector *connector,
        if (mode->clock < 10000)
                return MODE_CLOCK_LOW;
 
+       if ((target_clock > max_dotclk || mode->hdisplay > 5120) &&
+           intel_dp_can_bigjoiner(intel_dp)) {
+               bigjoiner = true;
+               max_dotclk *= 2;
+       }
+       if (target_clock > max_dotclk)
+               return MODE_CLOCK_HIGH;
+
        max_link_clock = intel_dp_max_link_rate(intel_dp);
        max_lanes = intel_dp_max_lane_count(intel_dp);
 
@@ -765,16 +809,23 @@ intel_dp_mode_valid(struct drm_connector *connector,
                                                            max_link_clock,
                                                            max_lanes,
                                                            target_clock,
-                                                           mode->hdisplay) >> 4;
+                                                           mode->hdisplay,
+                                                           bigjoiner) >> 4;
                        dsc_slice_count =
                                intel_dp_dsc_get_slice_count(intel_dp,
                                                             target_clock,
-                                                            mode->hdisplay);
+                                                            mode->hdisplay,
+                                                            bigjoiner);
                }
+
+               dsc = dsc_max_output_bpp && dsc_slice_count;
        }
 
-       if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
-           target_clock > max_dotclk)
+       /* big joiner configuration needs DSC */
+       if (bigjoiner && !dsc)
+               return MODE_CLOCK_HIGH;
+
+       if (mode_rate > max_rate && !dsc)
                return MODE_CLOCK_HIGH;
 
        status = intel_dp_mode_valid_downstream(intel_connector,
@@ -782,7 +833,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
        if (status != MODE_OK)
                return status;
 
-       return intel_mode_valid_max_plane_size(dev_priv, mode);
+       return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
 }
 
 u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
@@ -2351,11 +2402,13 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
                                                    pipe_config->port_clock,
                                                    pipe_config->lane_count,
                                                    adjusted_mode->crtc_clock,
-                                                   adjusted_mode->crtc_hdisplay);
+                                                   adjusted_mode->crtc_hdisplay,
+                                                   false);
                dsc_dp_slice_count =
                        intel_dp_dsc_get_slice_count(intel_dp,
                                                     adjusted_mode->crtc_clock,
-                                                    adjusted_mode->crtc_hdisplay);
+                                                    adjusted_mode->crtc_hdisplay,
+                                                    false);
                if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
                        drm_dbg_kms(&dev_priv->drm,
                                    "Compressed BPP/Slice Count not supported\n");

diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 3f862b4fd34f475c0f7f1e785bfdf1763dbf8939..b871a09b69013a398a4b19853f065afabf37ecc7 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -106,6 +106,7 @@ bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp);
 int intel_dp_link_required(int pixel_clock, int bpp);
 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
+bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp);
 bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
                            const struct drm_connector_state *conn_state);
 void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index c8fcec4d07885e08dd120a61619d5f54d4b2c572..0c8684634fca42b8e86a11f4e8b362cdbcac06d6 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -714,7 +714,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
                return 0;
        }
 
-       *status = intel_mode_valid_max_plane_size(dev_priv, mode);
+       *status = intel_mode_valid_max_plane_size(dev_priv, mode, false);
        return 0;
 }
 

diff --git a/drivers/gpu/drm/i915/display/intel_dsi.c b/drivers/gpu/drm/i915/display/intel_dsi.c
index afa4e6817e8c7be4fe0c96305ddee4a60005f722..f453ceb8d1494529ebe698ad58a7325c8151cd61 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dsi.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi.c
@@ -75,7 +75,7 @@ enum drm_mode_status intel_dsi_mode_valid(struct drm_connector *connector,
                        return MODE_CLOCK_HIGH;
        }
 
-       return intel_mode_valid_max_plane_size(dev_priv, mode);
+       return intel_mode_valid_max_plane_size(dev_priv, mode, false);
 }
 
 struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index f90838bc74fbcc189ae2f94ab6088af3d9ffc613..82674a8853c606e24f7b392786948fe1dcad4c6b 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2274,7 +2274,7 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
        if (status != MODE_OK)
                return status;
 
-       return intel_mode_valid_max_plane_size(dev_priv, mode);
+       return intel_mode_valid_max_plane_size(dev_priv, mode, false);
 }
 
 bool intel_hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,