drm/amdgpu: add gmc v10 supports for van gogh (v4)

Add gfx memory controller support for van gogh.

v2: don't use dynamic invalidate eng allocation for van gogh.
v3: squash in other fixes
v4: rebase

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index dbc8b76b9b78e650524775b95b3b1f06aae69ba6..d5b2dc61095c625fd22122353544770d7e447187 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -639,6 +639,7 @@ static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev)
        switch (adev->asic_type) {
        case CHIP_SIENNA_CICHLID:
        case CHIP_NAVY_FLOUNDER:
+       case CHIP_VANGOGH:
                adev->gfxhub.funcs = &gfxhub_v2_1_funcs;
                break;
        default:
@@ -733,6 +734,13 @@ static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
        adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
        adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
 
+#ifdef CONFIG_X86_64
+       if (adev->flags & AMD_IS_APU) {
+               adev->gmc.aper_base = adev->gfxhub.funcs->get_mc_fb_offset(adev);
+               adev->gmc.aper_size = adev->gmc.real_vram_size;
+       }
+#endif
+
        /* In case the PCI BAR is larger than the actual amount of vram */
        adev->gmc.visible_vram_size = adev->gmc.aper_size;
        if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
@@ -746,6 +754,7 @@ static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
                case CHIP_NAVI12:
                case CHIP_SIENNA_CICHLID:
                case CHIP_NAVY_FLOUNDER:
+               case CHIP_VANGOGH:
                default:
                        adev->gmc.gart_size = 512ULL << 20;
                        break;
@@ -790,7 +799,10 @@ static int gmc_v10_0_sw_init(void *handle)
 
        spin_lock_init(&adev->gmc.invalidate_lock);
 
-       if (adev->asic_type == CHIP_SIENNA_CICHLID && amdgpu_emu_mode == 1) {
+       if ((adev->flags & AMD_IS_APU) && amdgpu_emu_mode == 1) {
+               adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4;
+               adev->gmc.vram_width = 64;
+       } else if (amdgpu_emu_mode == 1) {
                adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6;
                adev->gmc.vram_width = 1 * 128; /* numchan * chansize */
        } else {
@@ -808,6 +820,7 @@ static int gmc_v10_0_sw_init(void *handle)
        case CHIP_NAVI12:
        case CHIP_SIENNA_CICHLID:
        case CHIP_NAVY_FLOUNDER:
+       case CHIP_VANGOGH:
                adev->num_vmhubs = 2;
                /*
                 * To fulfill 4-level page support,
@@ -921,6 +934,7 @@ static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev)
        case CHIP_NAVI12:
        case CHIP_SIENNA_CICHLID:
        case CHIP_NAVY_FLOUNDER:
+       case CHIP_VANGOGH:
                break;
        default:
                break;