arm64: dts: qcom: ipq6018: Pad addresses to 8 hex digits

Some addresses were 7-hex-digits long, or less. Fix that.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230102094642.74254-2-konrad.dybcio@linaro.org

diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index 2ceae73a6069e9f2d82a1fab9205cd49bcd818fb..6f12c1a8f90f365c18a0ac57aa5b8ba8e2119c60 100644 (file)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -146,7 +146,7 @@
                ranges;
 
                rpm_msg_ram: memory@60000 {
-                       reg = <0x0 0x60000 0x0 0x6000>;
+                       reg = <0x0 0x00060000 0x0 0x6000>;
                        no-map;
                };
 
@@ -181,7 +181,7 @@
 
                prng: qrng@e1000 {
                        compatible = "qcom,prng-ee";
-                       reg = <0x0 0xe3000 0x0 0x1000>;
+                       reg = <0x0 0x000e3000 0x0 0x1000>;
                        clocks = <&gcc GCC_PRNG_AHB_CLK>;
                        clock-names = "core";
                };
@@ -388,7 +388,7 @@
 
                pcie_phy: phy@84000 {
                        compatible = "qcom,ipq6018-qmp-pcie-phy";
-                       reg = <0x0 0x84000 0x0 0x1bc>; /* Serdes PLL */
+                       reg = <0x0 0x00084000 0x0 0x1bc>; /* Serdes PLL */
                        status = "disabled";
                        #address-cells = <2>;
                        #size-cells = <2>;
@@ -404,10 +404,10 @@
                                      "common";
 
                        pcie_phy0: phy@84200 {
-                               reg = <0x0 0x84200 0x0 0x16c>, /* Serdes Tx */
-                                     <0x0 0x84400 0x0 0x200>, /* Serdes Rx */
-                                     <0x0 0x84800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */
-                                     <0x0 0x84c00 0x0 0xf4>; /* pcs_misc */
+                               reg = <0x0 0x00084200 0x0 0x16c>, /* Serdes Tx */
+                                     <0x0 0x00084400 0x0 0x200>, /* Serdes Rx */
+                                     <0x0 0x00084800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */
+                                     <0x0 0x00084c00 0x0 0xf4>; /* pcs_misc */
                                #phy-cells = <0>;
 
                                clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
@@ -623,7 +623,7 @@
                        #address-cells = <1>;
                        #size-cells = <0>;
                        compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio";
-                       reg = <0x0 0x90000 0x0 0x64>;
+                       reg = <0x0 0x00090000 0x0 0x64>;
                        clocks = <&gcc GCC_MDIO_AHB_CLK>;
                        clock-names = "gcc_mdio_ahb_clk";
                        status = "disabled";
@@ -631,7 +631,7 @@
 
                qusb_phy_1: qusb@59000 {
                        compatible = "qcom,ipq6018-qusb2-phy";
-                       reg = <0x0 0x059000 0x0 0x180>;
+                       reg = <0x0 0x00059000 0x0 0x180>;
                        #phy-cells = <0>;
 
                        clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
@@ -664,7 +664,7 @@
 
                        dwc_1: usb@7000000 {
                               compatible = "snps,dwc3";
-                              reg = <0x0 0x7000000 0x0 0xcd00>;
+                              reg = <0x0 0x07000000 0x0 0xcd00>;
                               interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
                               phys = <&qusb_phy_1>;
                               phy-names = "usb2-phy";
@@ -679,7 +679,7 @@
 
                ssphy_0: ssphy@78000 {
                        compatible = "qcom,ipq6018-qmp-usb3-phy";
-                       reg = <0x0 0x78000 0x0 0x1c4>;
+                       reg = <0x0 0x00078000 0x0 0x1c4>;
                        #address-cells = <2>;
                        #size-cells = <2>;
                        ranges;
@@ -708,7 +708,7 @@
 
                qusb_phy_0: qusb@79000 {
                        compatible = "qcom,ipq6018-qusb2-phy";
-                       reg = <0x0 0x079000 0x0 0x180>;
+                       reg = <0x0 0x00079000 0x0 0x180>;
                        #phy-cells = <0>;
 
                        clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,