target/loongarch: Sign extend results in VA32 mode

In VA32 mode, BL, JIRL and PC* instructions should sign-extend the low
32 bit result to 64 bits.

Signed-off-by: Jiajie Chen <c@jia.je>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230822032724.1353391-7-gaosong@loongson.cn>
Message-Id: <20230822071959.35620-1-philmd@linaro.org>

diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
index 9a23ec786d6af66960486a749c0bb5d9ee2fd9af..de7c1c5d1f980b33d706b1a1c9db3680baacc72a 100644 (file)
--- a/target/loongarch/translate.c
+++ b/target/loongarch/translate.c
@@ -238,6 +238,9 @@ static TCGv make_address_i(DisasContext *ctx, TCGv base, target_long ofs)
 
 static uint64_t make_address_pc(DisasContext *ctx, uint64_t addr)
 {
+    if (ctx->va32) {
+        addr = (int32_t)addr;
+    }
     return addr;
 }