/* Apollolake */
        .cores_num = 2,
        .init_core_mask = 1,
-       .cores_mask = HDA_DSP_CORE_MASK(0) | HDA_DSP_CORE_MASK(1),
+       .host_managed_cores_mask = HDA_DSP_CORE_MASK(0) | HDA_DSP_CORE_MASK(1),
        .ipc_req = HDA_DSP_REG_HIPCI,
        .ipc_req_mask = HDA_DSP_REG_HIPCI_BUSY,
        .ipc_ack = HDA_DSP_REG_HIPCIE,
 
 
 const struct sof_intel_dsp_desc bdw_chip_info = {
        .cores_num = 1,
-       .cores_mask = 1,
+       .host_managed_cores_mask = 1,
 };
 EXPORT_SYMBOL_NS(bdw_chip_info, SND_SOC_SOF_BROADWELL);
 
 
 
 const struct sof_intel_dsp_desc tng_chip_info = {
        .cores_num = 1,
-       .cores_mask = 1,
+       .host_managed_cores_mask = 1,
 };
 EXPORT_SYMBOL_NS(tng_chip_info, SND_SOC_SOF_MERRIFIELD);
 
 
 const struct sof_intel_dsp_desc byt_chip_info = {
        .cores_num = 1,
-       .cores_mask = 1,
+       .host_managed_cores_mask = 1,
 };
 EXPORT_SYMBOL_NS(byt_chip_info, SND_SOC_SOF_BAYTRAIL);
 
 
 const struct sof_intel_dsp_desc cht_chip_info = {
        .cores_num = 1,
-       .cores_mask = 1,
+       .host_managed_cores_mask = 1,
 };
 EXPORT_SYMBOL_NS(cht_chip_info, SND_SOC_SOF_BAYTRAIL);
 
 
        /* Cannonlake */
        .cores_num = 4,
        .init_core_mask = 1,
-       .cores_mask = HDA_DSP_CORE_MASK(0) |
+       .host_managed_cores_mask = HDA_DSP_CORE_MASK(0) |
                                HDA_DSP_CORE_MASK(1) |
                                HDA_DSP_CORE_MASK(2) |
                                HDA_DSP_CORE_MASK(3),
        /* Icelake */
        .cores_num = 4,
        .init_core_mask = 1,
-       .cores_mask = HDA_DSP_CORE_MASK(0) |
+       .host_managed_cores_mask = HDA_DSP_CORE_MASK(0) |
                                HDA_DSP_CORE_MASK(1) |
                                HDA_DSP_CORE_MASK(2) |
                                HDA_DSP_CORE_MASK(3),
        /* Elkhartlake */
        .cores_num = 4,
        .init_core_mask = 1,
-       .cores_mask = HDA_DSP_CORE_MASK(0),
+       .host_managed_cores_mask = HDA_DSP_CORE_MASK(0),
        .ipc_req = CNL_DSP_REG_HIPCIDR,
        .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
        .ipc_ack = CNL_DSP_REG_HIPCIDA,
        /* Jasperlake */
        .cores_num = 2,
        .init_core_mask = 1,
-       .cores_mask = HDA_DSP_CORE_MASK(0) |
+       .host_managed_cores_mask = HDA_DSP_CORE_MASK(0) |
                                HDA_DSP_CORE_MASK(1),
        .ipc_req = CNL_DSP_REG_HIPCIDR,
        .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
 
 #endif
 
        /* power down DSP */
-       ret = hda_dsp_core_reset_power_down(sdev, chip->cores_mask);
+       ret = hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask);
        if (ret < 0) {
                dev_err(sdev->dev,
                        "error: failed to power down core during suspend\n");
 
        int i;
 
        /* step 1: power up corex */
-       ret = hda_dsp_core_power_up(sdev, chip->cores_mask);
+       ret = hda_dsp_core_power_up(sdev, chip->host_managed_cores_mask);
        if (ret < 0) {
                if (iteration == HDA_FW_BOOT_ATTEMPTS)
                        dev_err(sdev->dev, "error: dsp core 0/1 power up failed\n");
 
        /* step 5: power down corex */
        ret = hda_dsp_core_power_down(sdev,
-                                 chip->cores_mask & ~(HDA_DSP_CORE_MASK(0)));
+                                 chip->host_managed_cores_mask & ~(HDA_DSP_CORE_MASK(0)));
        if (ret < 0) {
                if (iteration == HDA_FW_BOOT_ATTEMPTS)
                        dev_err(sdev->dev,
 
 err:
        hda_dsp_dump(sdev, SOF_DBG_REGS | SOF_DBG_PCI | SOF_DBG_MBOX);
-       hda_dsp_core_reset_power_down(sdev, chip->cores_mask);
+       hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask);
 
        return ret;
 }
 
 
        /* disable cores */
        if (chip)
-               hda_dsp_core_reset_power_down(sdev, chip->cores_mask);
+               hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask);
 
        /* disable DSP */
        snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
 
 /* DSP hardware descriptor */
 struct sof_intel_dsp_desc {
        int cores_num;
-       int cores_mask;
+       int host_managed_cores_mask;
        int init_core_mask; /* cores available after fw boot */
        int ipc_req;
        int ipc_req_mask;
 
        /* Tigerlake */
        .cores_num = 4,
        .init_core_mask = 1,
-       .cores_mask = HDA_DSP_CORE_MASK(0),
+       .host_managed_cores_mask = HDA_DSP_CORE_MASK(0),
        .ipc_req = CNL_DSP_REG_HIPCIDR,
        .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
        .ipc_ack = CNL_DSP_REG_HIPCIDA,