ARM: dts: qcom-msm8974: Fix up SDHCI nodes
authorKonrad Dybcio <konrad.dybcio@somainline.org>
Fri, 15 Apr 2022 11:56:16 +0000 (13:56 +0200)
committerBjorn Andersson <bjorn.andersson@linaro.org>
Tue, 19 Apr 2022 23:22:16 +0000 (18:22 -0500)
- Add missing labels (and remove their redefinition from klte)
- Commonize bus-width
- Add non-removable on sdhc_1, as it's supposed to have an eMMC on it

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220415115633.575010-7-konrad.dybcio@somainline.org
arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts
arch/arm/boot/dts/qcom-msm8974.dtsi

index 95ae30d065542401537f6d272e42728bd66e5069..3ee2508b20fb9ca147366ff5caa6cbd729fa3167 100644 (file)
                };
        };
 
-       sdhc_1: sdhci@f9824900 {
+       sdhci@f9824900 {
                status = "okay";
 
                vmmc-supply = <&pma8084_l20>;
                pinctrl-0 = <&sdhc1_pin_a>;
        };
 
-       sdhc_2: sdhci@f9864900 {
+       sdhci@f9864900 {
                status = "okay";
 
                max-frequency = <100000000>;
index 636d68a6f60322a4fa15ac45030436774785fba0..49b22392fd5e0ba20dcafff5cb0c31db580f2eca 100644 (file)
                        status = "disabled";
                };
 
-               sdhci@f9824900 {
+               sdhc_1: sdhci@f9824900 {
                        compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
                        reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
                        reg-names = "hc_mem", "core_mem";
                                 <&gcc GCC_SDCC1_AHB_CLK>,
                                 <&xo_board>;
                        clock-names = "core", "iface", "xo";
+                       bus-width = <8>;
+                       non-removable;
+
                        status = "disabled";
                };
 
-               sdhci@f9864900 {
+               sdhc_3: sdhci@f9864900 {
                        compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
                        reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
                        reg-names = "hc_mem", "core_mem";
                                 <&gcc GCC_SDCC3_AHB_CLK>,
                                 <&xo_board>;
                        clock-names = "core", "iface", "xo";
+                       bus-width = <4>;
+
                        status = "disabled";
                };
 
-               sdhci@f98a4900 {
+               sdhc_2: sdhci@f98a4900 {
                        compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
                        reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
                        reg-names = "hc_mem", "core_mem";
                                 <&gcc GCC_SDCC2_AHB_CLK>,
                                 <&xo_board>;
                        clock-names = "core", "iface", "xo";
+                       bus-width = <4>;
+
                        status = "disabled";
                };