riscv: errata: Add StarFive JH7100 errata

This not really an errata, but since the JH7100 was made before
the standard Zicbom extension it needs the DMA_GLOBAL_POOL and
RISCV_NONSTANDARD_CACHE_OPS enabled to work correctly.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
index e2c731cfed8cc6e878a6fed176cc82ae79b2fbfb..692de149141fcd97478c764562684b701b8f039d 100644 (file)
--- a/arch/riscv/Kconfig.errata
+++ b/arch/riscv/Kconfig.errata
@@ -53,6 +53,23 @@ config ERRATA_SIFIVE_CIP_1200
 
          If you don't know what to do here, say "Y".
 
+config ERRATA_STARFIVE_JH7100
+       bool "StarFive JH7100 support"
+       depends on ARCH_STARFIVE && NONPORTABLE
+       select DMA_GLOBAL_POOL
+       select RISCV_DMA_NONCOHERENT
+       select RISCV_NONSTANDARD_CACHE_OPS
+       select SIFIVE_CCACHE
+       default n
+       help
+         The StarFive JH7100 was a test chip for the JH7110 and has
+         caches that are non-coherent with respect to peripheral DMAs.
+         It was designed before the Zicbom extension so needs non-standard
+         cache operations through the SiFive cache controller.
+
+         Say "Y" if you want to support the BeagleV Starlight and/or
+         StarFive VisionFive V1 boards.
+
 config ERRATA_THEAD
        bool "T-HEAD errata"
        depends on RISCV_ALTERNATIVE