drm/amdgpu: save the reset dump register value for devcoredump
authorSomalapuram Amaranath <Amaranath.Somalapuram@amd.com>
Thu, 2 Jun 2022 07:24:58 +0000 (12:54 +0530)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 6 Jun 2022 18:41:12 +0000 (14:41 -0400)
Allocate memory for register value and use the same values for devcoredump.
v1 -> v2: Change krealloc_array() to kmalloc_array()
v2 -> v3: Fix alignment

Signed-off-by: Somalapuram Amaranath <Amaranath.Somalapuram@amd.com>
Reviewed-by: Shashank Sharma <Shashank.sharma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu.h
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

index 3ec7427c018c9ae303f87bfe2d6e58f92903651f..1525fa1d6798bc821126979b5fd6c260c408078f 100644 (file)
@@ -1044,6 +1044,7 @@ struct amdgpu_device {
 
        /* reset dump register */
        uint32_t                        *reset_dump_reg_list;
+       uint32_t                        *reset_dump_reg_value;
        int                             num_regs;
 
        bool                            scpm_enabled;
index eedb12f6b8a32df4e223c643cc607cd176788a08..f3ac7912c29c471c971d85f56108efc425e26ac4 100644 (file)
@@ -1709,17 +1709,24 @@ static ssize_t amdgpu_reset_dump_register_list_write(struct file *f,
                i++;
        } while (len < size);
 
+       new = kmalloc_array(i, sizeof(uint32_t), GFP_KERNEL);
+       if (!new) {
+               ret = -ENOMEM;
+               goto error_free;
+       }
        ret = down_write_killable(&adev->reset_domain->sem);
        if (ret)
                goto error_free;
 
        swap(adev->reset_dump_reg_list, tmp);
+       swap(adev->reset_dump_reg_value, new);
        adev->num_regs = i;
        up_write(&adev->reset_domain->sem);
        ret = size;
 
 error_free:
        kfree(tmp);
+       kfree(new);
        return ret;
 }
 
index 4831148342b75eee17c3ff42936056a6c7f99eae..c56b04e9ce9a9460088a86c8e478fa1accb0be69 100644 (file)
@@ -4666,15 +4666,15 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
 
 static int amdgpu_reset_reg_dumps(struct amdgpu_device *adev)
 {
-       uint32_t reg_value;
        int i;
 
        lockdep_assert_held(&adev->reset_domain->sem);
        dump_stack();
 
        for (i = 0; i < adev->num_regs; i++) {
-               reg_value = RREG32(adev->reset_dump_reg_list[i]);
-               trace_amdgpu_reset_reg_dumps(adev->reset_dump_reg_list[i], reg_value);
+               adev->reset_dump_reg_value[i] = RREG32(adev->reset_dump_reg_list[i]);
+               trace_amdgpu_reset_reg_dumps(adev->reset_dump_reg_list[i],
+                                            adev->reset_dump_reg_value[i]);
        }
 
        return 0;