#include <asm/fpu.h>
 #include <asm/mipsregs.h>
 #include <asm/system.h>
+#include <asm/watch.h>
 
 /*
  * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
 {
        decode_configs(c);
+       mips_probe_watch_registers(c);
        switch (c->processor_id & 0xff00) {
        case PRID_IMP_4KC:
                c->cputype = CPU_4KC;
 
        unsigned int version = cpu_data[n].processor_id;
        unsigned int fp_vers = cpu_data[n].fpu_id;
        char fmt [64];
+       int i;
 
 #ifdef CONFIG_SMP
        if (!cpu_isset(n, cpu_online_map))
        seq_printf(m, "tlb_entries\t\t: %d\n", cpu_data[n].tlbsize);
        seq_printf(m, "extra interrupt vector\t: %s\n",
                      cpu_has_divec ? "yes" : "no");
-       seq_printf(m, "hardware watchpoint\t: %s\n",
-                     cpu_has_watch ? "yes" : "no");
+       seq_printf(m, "hardware watchpoint\t: %s",
+                  cpu_has_watch ? "yes, " : "no\n");
+       if (cpu_has_watch) {
+               seq_printf(m, "count: %d, address/irw mask: [",
+                          cpu_data[n].watch_reg_count);
+               for (i = 0; i < cpu_data[n].watch_reg_count; i++)
+                       seq_printf(m, "%s0x%04x", i ? ", " : "" ,
+                                  cpu_data[n].watch_reg_masks[i]);
+               seq_printf(m, "]\n");
+       }
        seq_printf(m, "ASEs implemented\t:%s%s%s%s%s%s\n",
                      cpu_has_mips16 ? " mips16" : "",
                      cpu_has_mdmx ? " mdmx" : "",