extern void e500_idle(void);
extern void power4_idle(void);
extern void ppc6xx_idle(void);
-extern void book3e_idle(void);
/*
* ppc_md contains a copy of the machine description structure for the
obj-$(CONFIG_PPC_BOOK3S_64) += cpu_setup_ppc970.o cpu_setup_pa6t.o
obj-$(CONFIG_PPC_BOOK3S_64) += cpu_setup_power.o
obj-$(CONFIG_PPC_BOOK3S_64) += mce.o mce_power.o
-obj-$(CONFIG_PPC_BOOK3E_64) += exceptions-64e.o idle_book3e.o
+obj-$(CONFIG_PPC_BOOK3E_64) += exceptions-64e.o idle_64e.o
obj-$(CONFIG_PPC_BARRIER_NOSPEC) += security.o
obj-$(CONFIG_PPC64) += vdso64_wrapper.o
obj-$(CONFIG_ALTIVEC) += vecemu.o
obj-$(CONFIG_CRASH_DUMP) += crash_dump.o
obj-$(CONFIG_FA_DUMP) += fadump.o
obj-$(CONFIG_PRESERVE_FA_DUMP) += fadump.o
-ifdef CONFIG_PPC32
-obj-$(CONFIG_PPC_E500) += idle_e500.o
-endif
+obj-$(CONFIG_PPC_85xx) += idle_85xx.o
obj-$(CONFIG_PPC_BOOK3S_32) += idle_6xx.o l2cr_6xx.o cpu_setup_6xx.o
obj-$(CONFIG_TAU) += tau_6xx.o
obj-$(CONFIG_HIBERNATION) += swsusp.o suspend.o
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright 2010 IBM Corp, Benjamin Herrenschmidt <benh@kernel.crashing.org>
+ *
+ * Generic idle routine for 64 bits e500 processors
+ */
+
+#include <linux/threads.h>
+#include <asm/reg.h>
+#include <asm/ppc_asm.h>
+#include <asm/asm-offsets.h>
+#include <asm/ppc-opcode.h>
+#include <asm/processor.h>
+#include <asm/thread_info.h>
+#include <asm/epapr_hcalls.h>
+#include <asm/hw_irq.h>
+
+/* 64-bit version only for now */
+.macro BOOK3E_IDLE name loop
+_GLOBAL(\name)
+ /* Save LR for later */
+ mflr r0
+ std r0,16(r1)
+
+ /* Hard disable interrupts */
+ wrteei 0
+
+ /* Now check if an interrupt came in while we were soft disabled
+ * since we may otherwise lose it (doorbells etc...).
+ */
+ lbz r3,PACAIRQHAPPENED(r13)
+ cmpwi cr0,r3,0
+ bne 2f
+
+ /* Now we are going to mark ourselves as soft and hard enabled in
+ * order to be able to take interrupts while asleep. We inform lockdep
+ * of that. We don't actually turn interrupts on just yet tho.
+ */
+#ifdef CONFIG_TRACE_IRQFLAGS
+ stdu r1,-128(r1)
+ bl trace_hardirqs_on
+ addi r1,r1,128
+#endif
+ li r0,IRQS_ENABLED
+ stb r0,PACAIRQSOFTMASK(r13)
+
+ /* Interrupts will make use return to LR, so get something we want
+ * in there
+ */
+ bl 1f
+
+ /* And return (interrupts are on) */
+ ld r0,16(r1)
+ mtlr r0
+ blr
+
+1: /* Let's set the _TLF_NAPPING flag so interrupts make us return
+ * to the right spot
+ */
+ ld r11, PACACURRENT(r13)
+ ld r10,TI_LOCAL_FLAGS(r11)
+ ori r10,r10,_TLF_NAPPING
+ std r10,TI_LOCAL_FLAGS(r11)
+
+ /* We can now re-enable hard interrupts and go to sleep */
+ wrteei 1
+ \loop
+
+2:
+ lbz r10,PACAIRQHAPPENED(r13)
+ ori r10,r10,PACA_IRQ_HARD_DIS
+ stb r10,PACAIRQHAPPENED(r13)
+ blr
+.endm
+
+.macro BOOK3E_IDLE_LOOP
+1:
+ PPC_WAIT(0)
+ b 1b
+.endm
+
+/* epapr_ev_idle_start below is patched with the proper hcall
+ opcodes during kernel initialization */
+.macro EPAPR_EV_IDLE_LOOP
+idle_loop:
+ LOAD_REG_IMMEDIATE(r11, EV_HCALL_TOKEN(EV_IDLE))
+
+.global epapr_ev_idle_start
+epapr_ev_idle_start:
+ li r3, -1
+ nop
+ nop
+ nop
+ b idle_loop
+.endm
+
+BOOK3E_IDLE epapr_ev_idle EPAPR_EV_IDLE_LOOP
+
+BOOK3E_IDLE e500_idle BOOK3E_IDLE_LOOP
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2008 Freescale Semiconductor, Inc. All rights reserved.
+ * Dave Liu <daveliu@freescale.com>
+ * copy from idle_6xx.S and modify for e500 based processor,
+ * implement the power_save function in idle.
+ */
+
+#include <linux/threads.h>
+#include <asm/reg.h>
+#include <asm/page.h>
+#include <asm/cputable.h>
+#include <asm/thread_info.h>
+#include <asm/ppc_asm.h>
+#include <asm/asm-offsets.h>
+#include <asm/feature-fixups.h>
+
+ .text
+
+_GLOBAL(e500_idle)
+ lwz r4,TI_LOCAL_FLAGS(r2) /* set napping bit */
+ ori r4,r4,_TLF_NAPPING /* so when we take an exception */
+ stw r4,TI_LOCAL_FLAGS(r2) /* it will return to our caller */
+
+#ifdef CONFIG_PPC_E500MC
+ wrteei 1
+1: wait
+
+ /*
+ * Guard against spurious wakeups (e.g. from a hypervisor) --
+ * any real interrupt will cause us to return to LR due to
+ * _TLF_NAPPING.
+ */
+ b 1b
+#else
+ /* Check if we can nap or doze, put HID0 mask in r3 */
+ lis r3,0
+BEGIN_FTR_SECTION
+ lis r3,HID0_DOZE@h
+END_FTR_SECTION_IFSET(CPU_FTR_CAN_DOZE)
+
+BEGIN_FTR_SECTION
+ /* Now check if user enabled NAP mode */
+ lis r4,powersave_nap@ha
+ lwz r4,powersave_nap@l(r4)
+ cmpwi 0,r4,0
+ beq 1f
+ stwu r1,-16(r1)
+ mflr r0
+ stw r0,20(r1)
+ bl flush_dcache_L1
+ lwz r0,20(r1)
+ addi r1,r1,16
+ mtlr r0
+ lis r3,HID0_NAP@h
+END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
+1:
+ /* Go to NAP or DOZE now */
+ mfspr r4,SPRN_HID0
+ rlwinm r4,r4,0,~(HID0_DOZE|HID0_NAP|HID0_SLEEP)
+ or r4,r4,r3
+ isync
+ mtspr SPRN_HID0,r4
+ isync
+
+ mfmsr r7
+ oris r7,r7,MSR_WE@h
+ ori r7,r7,MSR_EE
+ msync
+ mtmsr r7
+ isync
+2: b 2b
+#endif /* !E500MC */
+
+/*
+ * Return from NAP/DOZE mode, restore some CPU specific registers,
+ * r2 containing address of current.
+ * r11 points to the exception frame.
+ * We have to preserve r10.
+ */
+_GLOBAL(power_save_ppc32_restore)
+ lwz r9,_LINK(r11) /* interrupted in e500_idle */
+ stw r9,_NIP(r11) /* make it do a blr */
+ blr
+_ASM_NOKPROBE_SYMBOL(power_save_ppc32_restore)
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Copyright 2010 IBM Corp, Benjamin Herrenschmidt <benh@kernel.crashing.org>
- *
- * Generic idle routine for Book3E processors
- */
-
-#include <linux/threads.h>
-#include <asm/reg.h>
-#include <asm/ppc_asm.h>
-#include <asm/asm-offsets.h>
-#include <asm/ppc-opcode.h>
-#include <asm/processor.h>
-#include <asm/thread_info.h>
-#include <asm/epapr_hcalls.h>
-#include <asm/hw_irq.h>
-
-/* 64-bit version only for now */
-#ifdef CONFIG_PPC64
-
-.macro BOOK3E_IDLE name loop
-_GLOBAL(\name)
- /* Save LR for later */
- mflr r0
- std r0,16(r1)
-
- /* Hard disable interrupts */
- wrteei 0
-
- /* Now check if an interrupt came in while we were soft disabled
- * since we may otherwise lose it (doorbells etc...).
- */
- lbz r3,PACAIRQHAPPENED(r13)
- cmpwi cr0,r3,0
- bne 2f
-
- /* Now we are going to mark ourselves as soft and hard enabled in
- * order to be able to take interrupts while asleep. We inform lockdep
- * of that. We don't actually turn interrupts on just yet tho.
- */
-#ifdef CONFIG_TRACE_IRQFLAGS
- stdu r1,-128(r1)
- bl trace_hardirqs_on
- addi r1,r1,128
-#endif
- li r0,IRQS_ENABLED
- stb r0,PACAIRQSOFTMASK(r13)
-
- /* Interrupts will make use return to LR, so get something we want
- * in there
- */
- bl 1f
-
- /* And return (interrupts are on) */
- ld r0,16(r1)
- mtlr r0
- blr
-
-1: /* Let's set the _TLF_NAPPING flag so interrupts make us return
- * to the right spot
- */
- ld r11, PACACURRENT(r13)
- ld r10,TI_LOCAL_FLAGS(r11)
- ori r10,r10,_TLF_NAPPING
- std r10,TI_LOCAL_FLAGS(r11)
-
- /* We can now re-enable hard interrupts and go to sleep */
- wrteei 1
- \loop
-
-2:
- lbz r10,PACAIRQHAPPENED(r13)
- ori r10,r10,PACA_IRQ_HARD_DIS
- stb r10,PACAIRQHAPPENED(r13)
- blr
-.endm
-
-.macro BOOK3E_IDLE_LOOP
-1:
- PPC_WAIT(0)
- b 1b
-.endm
-
-/* epapr_ev_idle_start below is patched with the proper hcall
- opcodes during kernel initialization */
-.macro EPAPR_EV_IDLE_LOOP
-idle_loop:
- LOAD_REG_IMMEDIATE(r11, EV_HCALL_TOKEN(EV_IDLE))
-
-.global epapr_ev_idle_start
-epapr_ev_idle_start:
- li r3, -1
- nop
- nop
- nop
- b idle_loop
-.endm
-
-BOOK3E_IDLE epapr_ev_idle EPAPR_EV_IDLE_LOOP
-
-BOOK3E_IDLE book3e_idle BOOK3E_IDLE_LOOP
-
-#endif /* CONFIG_PPC64 */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Copyright (C) 2008 Freescale Semiconductor, Inc. All rights reserved.
- * Dave Liu <daveliu@freescale.com>
- * copy from idle_6xx.S and modify for e500 based processor,
- * implement the power_save function in idle.
- */
-
-#include <linux/threads.h>
-#include <asm/reg.h>
-#include <asm/page.h>
-#include <asm/cputable.h>
-#include <asm/thread_info.h>
-#include <asm/ppc_asm.h>
-#include <asm/asm-offsets.h>
-#include <asm/feature-fixups.h>
-
- .text
-
-_GLOBAL(e500_idle)
- lwz r4,TI_LOCAL_FLAGS(r2) /* set napping bit */
- ori r4,r4,_TLF_NAPPING /* so when we take an exception */
- stw r4,TI_LOCAL_FLAGS(r2) /* it will return to our caller */
-
-#ifdef CONFIG_PPC_E500MC
- wrteei 1
-1: wait
-
- /*
- * Guard against spurious wakeups (e.g. from a hypervisor) --
- * any real interrupt will cause us to return to LR due to
- * _TLF_NAPPING.
- */
- b 1b
-#else
- /* Check if we can nap or doze, put HID0 mask in r3 */
- lis r3,0
-BEGIN_FTR_SECTION
- lis r3,HID0_DOZE@h
-END_FTR_SECTION_IFSET(CPU_FTR_CAN_DOZE)
-
-BEGIN_FTR_SECTION
- /* Now check if user enabled NAP mode */
- lis r4,powersave_nap@ha
- lwz r4,powersave_nap@l(r4)
- cmpwi 0,r4,0
- beq 1f
- stwu r1,-16(r1)
- mflr r0
- stw r0,20(r1)
- bl flush_dcache_L1
- lwz r0,20(r1)
- addi r1,r1,16
- mtlr r0
- lis r3,HID0_NAP@h
-END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
-1:
- /* Go to NAP or DOZE now */
- mfspr r4,SPRN_HID0
- rlwinm r4,r4,0,~(HID0_DOZE|HID0_NAP|HID0_SLEEP)
- or r4,r4,r3
- isync
- mtspr SPRN_HID0,r4
- isync
-
- mfmsr r7
- oris r7,r7,MSR_WE@h
- ori r7,r7,MSR_EE
- msync
- mtmsr r7
- isync
-2: b 2b
-#endif /* !E500MC */
-
-/*
- * Return from NAP/DOZE mode, restore some CPU specific registers,
- * r2 containing address of current.
- * r11 points to the exception frame.
- * We have to preserve r10.
- */
-_GLOBAL(power_save_ppc32_restore)
- lwz r9,_LINK(r11) /* interrupted in e500_idle */
- stw r9,_NIP(r11) /* make it do a blr */
- blr
-_ASM_NOKPROBE_SYMBOL(power_save_ppc32_restore)
#endif
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
-#ifdef CONFIG_PPC64
- .power_save = book3e_idle,
-#else
.power_save = e500_idle,
-#endif
};
.get_irq = mpic_get_coreint_irq,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
-#ifdef CONFIG_PPC64
- .power_save = book3e_idle,
-#else
.power_save = e500_idle,
-#endif
};
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