watchdog: s3c2410_wdt: Add support for WTCON register DBGACK_MASK bit

The WDT uses the CPU core signal DBGACK to determine whether the SoC
is running in debug mode or not. If the DBGACK signal is asserted and
DBGACK_MASK bit is enabled, then WDT output and interrupt is masked
(disabled).

Presence of the DBGACK_MASK bit is determined by adding a new
QUIRK_HAS_DBGACK_BIT quirk. Also update to use BIT macro to avoid
checkpatch --strict warnings.

Tested-by: Will McVicker <willmcvicker@google.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20231211162331.435900-11-peter.griffin@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
index 0b4bd883ff28a8a03572c86b0b2717aaba9d58bc..7ecb762a371dd9fd8d3a3eac5bed222ed2fd5e32 100644 (file)
--- a/drivers/watchdog/s3c2410_wdt.c
+++ b/drivers/watchdog/s3c2410_wdt.c
@@ -9,6 +9,7 @@
  *     (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>
  */
 
+#include <linux/bits.h>
 #include <linux/module.h>
 #include <linux/moduleparam.h>
 #include <linux/types.h>
@@ -34,9 +35,10 @@
 
 #define S3C2410_WTCNT_MAXCNT   0xffff
 
-#define S3C2410_WTCON_RSTEN    (1 << 0)
-#define S3C2410_WTCON_INTEN    (1 << 2)
-#define S3C2410_WTCON_ENABLE   (1 << 5)
+#define S3C2410_WTCON_RSTEN            BIT(0)
+#define S3C2410_WTCON_INTEN            BIT(2)
+#define S3C2410_WTCON_ENABLE           BIT(5)
+#define S3C2410_WTCON_DBGACK_MASK      BIT(16)
 
 #define S3C2410_WTCON_DIV16    (0 << 3)
 #define S3C2410_WTCON_DIV32    (1 << 3)
@@ -100,12 +102,17 @@
  * %QUIRK_HAS_PMU_CNT_EN: PMU block has some register (e.g. CLUSTERx_NONCPU_OUT)
  * with "watchdog counter enable" bit. That bit should be set to make watchdog
  * counter running.
+ *
+ * %QUIRK_HAS_DBGACK_BIT: WTCON register has DBGACK_MASK bit. Setting the
+ * DBGACK_MASK bit disables the watchdog outputs when the SoC is in debug mode.
+ * Debug mode is determined by the DBGACK CPU signal.
  */
 #define QUIRK_HAS_WTCLRINT_REG                 (1 << 0)
 #define QUIRK_HAS_PMU_MASK_RESET               (1 << 1)
 #define QUIRK_HAS_PMU_RST_STAT                 (1 << 2)
 #define QUIRK_HAS_PMU_AUTO_DISABLE             (1 << 3)
 #define QUIRK_HAS_PMU_CNT_EN                   (1 << 4)
+#define QUIRK_HAS_DBGACK_BIT                   BIT(5)
 
 /* These quirks require that we have a PMU register map */
 #define QUIRKS_HAVE_PMUREG \
@@ -375,6 +382,19 @@ static int s3c2410wdt_enable(struct s3c2410_wdt *wdt, bool en)
        return 0;
 }
 
+/* Disable watchdog outputs if CPU is in debug mode */
+static void s3c2410wdt_mask_dbgack(struct s3c2410_wdt *wdt)
+{
+       unsigned long wtcon;
+
+       if (!(wdt->drv_data->quirks & QUIRK_HAS_DBGACK_BIT))
+               return;
+
+       wtcon = readl(wdt->reg_base + S3C2410_WTCON);
+       wtcon |= S3C2410_WTCON_DBGACK_MASK;
+       writel(wtcon, wdt->reg_base + S3C2410_WTCON);
+}
+
 static int s3c2410wdt_keepalive(struct watchdog_device *wdd)
 {
        struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
@@ -700,6 +720,8 @@ static int s3c2410wdt_probe(struct platform_device *pdev)
        wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt);
        wdt->wdt_device.parent = dev;
 
+       s3c2410wdt_mask_dbgack(wdt);
+
        /*
         * If "tmr_atboot" param is non-zero, start the watchdog right now. Also
         * set WDOG_HW_RUNNING bit, so that watchdog core can kick the watchdog.