arm64: dts: qcom: sm8450: add display clock controller

Add device node for display clock controller on Qualcomm SM8450 platform

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220908222850.3552050-5-dmitry.baryshkov@linaro.org

diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 7569ef1339a9348d136fbe760b04ae79904178e4..eeff62d0954b8bf02dd6d51178a39e1a443731f6 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -7,6 +7,7 @@
 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/clock/qcom,sm8450-camcc.h>
+#include <dt-bindings/clock/qcom,sm8450-dispcc.h>
 #include <dt-bindings/dma/qcom-gpi.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/mailbox/qcom-ipcc.h>
@@ -2400,6 +2401,33 @@
                        status = "disabled";
                };
 
+               dispcc: clock-controller@af00000 {
+                       compatible = "qcom,sm8450-dispcc";
+                       reg = <0 0x0af00000 0 0x20000>;
+                       clocks = <&rpmhcc RPMH_CXO_CLK>,
+                                <&rpmhcc RPMH_CXO_CLK_A>,
+                                <&gcc GCC_DISP_AHB_CLK>,
+                                <&sleep_clk>,
+                                <0>, /* dsi0 */
+                                <0>,
+                                <0>, /* dsi1 */
+                                <0>,
+                                <0>, /* dp0 */
+                                <0>,
+                                <0>, /* dp1 */
+                                <0>,
+                                <0>, /* dp2 */
+                                <0>,
+                                <0>, /* dp3 */
+                                <0>;
+                       power-domains = <&rpmhpd SM8450_MMCX>;
+                       required-opps = <&rpmhpd_opp_low_svs>;
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+                       #power-domain-cells = <1>;
+                       status = "disabled";
+               };
+
                pdc: interrupt-controller@b220000 {
                        compatible = "qcom,sm8450-pdc", "qcom,pdc";
                        reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;