clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>,
<&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;
clock-names = "ref_clk", "phy_clk";
- freq-table-hz = <0 0
- 0 0>;
+ freq-table-hz = <0 0>,
+ <0 0>;
/* offset: 0x84; bit: 12 */
resets = <&crg_rst 0x84 12>;
reset-names = "rst";
clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>,
<&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>;
clock-names = "ref_clk", "phy_clk";
- freq-table-hz = <0 0
- 0 0>;
+ freq-table-hz = <0 0>,
+ <0 0>;
/* offset: 0x84; bit: 12 */
resets = <&crg_rst 0x84 12>;
reset-names = "rst";