arm64: dts: qcom: sm6350: Fix the base addresses of LLCC banks

The LLCC block has several banks each with a different base address
and holes in between. So it is not a correct approach to cover these
banks with a single offset/size. Instead, the individual bank's base
address needs to be specified in devicetree with the exact size.

On SM6350, there is only one LLCC bank available. So let's just pass that
as "llcc0_base".

Reported-by: Parikshit Pareek <quic_ppareek@quicinc.com>
Tested-by: Luca Weiss <luca.weiss@fairphone.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230314080443.64635-12-manivannan.sadhasivam@linaro.org

diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index c46bb6dab6a10203398bb1aee105dd4fabdb4c28..318fefc8f4fa926f290eaf9549055d849f40c309 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -1356,7 +1356,7 @@
                system-cache-controller@9200000 {
                        compatible = "qcom,sm6350-llcc";
                        reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
-                       reg-names = "llcc_base", "llcc_broadcast_base";
+                       reg-names = "llcc0_base", "llcc_broadcast_base";
                };
 
                gem_noc: interconnect@9680000 {