riscv: dts: starfive: jh7100: Add temperature sensor node and thermal-zones

Add temperature sensor and thermal-zones support for
the StarFive JH7100 SoC.

Co-developed-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
index 4218621ea3b92c90a6b8b81bc4015649cc7eda3e..35ab54fb235fa27ea34bbf706eb87361710d80c6 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
@@ -80,6 +80,31 @@
                };
        };
 
+       thermal-zones {
+               cpu-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <15000>;
+
+                       thermal-sensors = <&sfctemp>;
+
+                       trips {
+                               cpu_alert0 {
+                                       /* milliCelsius */
+                                       temperature = <75000>;
+                                       hysteresis = <2000>;
+                                       type = "passive";
+                               };
+
+                               cpu_crit {
+                                       /* milliCelsius */
+                                       temperature = <90000>;
+                                       hysteresis = <2000>;
+                                       type = "critical";
+                               };
+                       };
+               };
+       };
+
        osc_sys: osc_sys {
                compatible = "fixed-clock";
                #clock-cells = <0>;
@@ -248,5 +273,17 @@
                        resets = <&rstgen JH7100_RSTN_WDTIMER_APB>,
                                 <&rstgen JH7100_RSTN_WDT>;
                };
+
+               sfctemp: temperature-sensor@124a0000 {
+                       compatible = "starfive,jh7100-temp";
+                       reg = <0x0 0x124a0000 0x0 0x10000>;
+                       clocks = <&clkgen JH7100_CLK_TEMP_SENSE>,
+                                <&clkgen JH7100_CLK_TEMP_APB>;
+                       clock-names = "sense", "bus";
+                       resets = <&rstgen JH7100_RSTN_TEMP_SENSE>,
+                                <&rstgen JH7100_RSTN_TEMP_APB>;
+                       reset-names = "sense", "bus";
+                       #thermal-sensor-cells = <0>;
+               };
        };
 };