coresight: etm4x: Cleanup TRCSSPCICRn register accesses

This is a no-op change for style and consistency and has no effect on
the binary output by the compiler. In sysreg.h fields are defined as
the register name followed by the field name and then _MASK. This
allows for grepping for fields by name rather than using magic numbers.

Signed-off-by: James Clark <james.clark@arm.com>
Reviewed-by: Mike Leach <mike.leach@linaro.org>
Link: https://lore.kernel.org/r/20220304171913.2292458-14-james.clark@arm.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
index 7dd7636fc2a7be75ef47baa34fc47cca680425c2..25f76a656308ea379da74627de392e3009cf1a65 100644 (file)
--- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
@@ -1842,7 +1842,7 @@ static ssize_t sshot_pe_ctrl_store(struct device *dev,
 
        spin_lock(&drvdata->spinlock);
        idx = config->ss_idx;
-       config->ss_pe_cmp[idx] = val & GENMASK(7, 0);
+       config->ss_pe_cmp[idx] = FIELD_PREP(TRCSSPCICRn_PC_MASK, val);
        /* must clear bit 31 in related status register on programming */
        config->ss_status[idx] &= ~TRCSSCSRn_STATUS;
        spin_unlock(&drvdata->spinlock);

diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
index b4217eaab4505e998a1c68312582575e4e717ecf..3b81c104a44b0f25043971b41a5319f56e380c8f 100644 (file)
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
@@ -218,6 +218,8 @@
 #define TRCSSCSRn_STATUS                       BIT(31)
 #define TRCSSCCRn_SAC_ARC_RST_MASK             GENMASK(24, 0)
 
+#define TRCSSPCICRn_PC_MASK                    GENMASK(7, 0)
+
 /*
  * System instructions to access ETM registers.
  * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions