clk: rockchip: rk3568: Add PLL rate for 126.4MHz

Add support for a PLL rate of 126.4MHz so that the Powkiddy X55 panel
can run at a requested 60hz.

I have confirmed this rate fits with all the constraints
listed in the TRM for the VPLL (as an integer PLL) in Part 1 "Chapter
2 Clock & Reset Unit (CRU)."

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Link: https://lore.kernel.org/r/20231204185719.569021-9-macroalpha82@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
index 43185668daf63131726ea8950be1b52c8b746518..497a7e51ffda4437ca4525a2849d6e6232293387 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3568.c
+++ b/drivers/clk/rockchip/clk-rk3568.c
@@ -77,6 +77,7 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
        RK3036_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0),
        RK3036_PLL_RATE(148500000, 1, 99, 4, 4, 1, 0),
        RK3036_PLL_RATE(135000000, 2, 45, 4, 1, 1, 0),
+       RK3036_PLL_RATE(126400000, 1, 79, 5, 3, 1, 0),
        RK3036_PLL_RATE(119000000, 3, 119, 4, 2, 1, 0),
        RK3036_PLL_RATE(115200000, 1, 24, 5, 1, 1, 0),
        RK3036_PLL_RATE(108000000, 2, 45, 5, 1, 1, 0),