staging: r8188eu: move pwr seq defines to HalPwrSeqCmd.c

The power sequences are now defined and processed in the same file. We
can move the defines for power sequences and the related struct and
enum from HalPwrSeqCmd.h to HalPwrSeqCmd.c. They don't have to be visible
in other files any more.

Tested-by: Philipp Hortmann <philipp.g.hortmann@gmail.com> # Edimax N150
Signed-off-by: Martin Kaiser <martin@kaiser.cx>
Link: https://lore.kernel.org/r/20220704145221.159949-2-martin@kaiser.cx
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/staging/r8188eu/hal/HalPwrSeqCmd.c b/drivers/staging/r8188eu/hal/HalPwrSeqCmd.c
index 5b0f66573d94ded246aaa98b12ed5c8fb5cc3a37..fb8eeaf51afa0a2023fe8f7c2bde34c3583cc0d3 100644 (file)
--- a/drivers/staging/r8188eu/hal/HalPwrSeqCmd.c
+++ b/drivers/staging/r8188eu/hal/HalPwrSeqCmd.c
@@ -3,6 +3,49 @@
 
 #include "../include/HalPwrSeqCmd.h"
 
+#define PWR_CMD_WRITE                  0x01
+     /*  offset: the read register offset */
+     /*  msk: the mask of the write bits */
+     /*  value: write value */
+     /*  note: driver shall implement this cmd by read & msk after write */
+
+#define PWR_CMD_POLLING                        0x02
+     /*  offset: the read register offset */
+     /*  msk: the mask of the polled value */
+     /*  value: the value to be polled, masked by the msd field. */
+     /*  note: driver shall implement this cmd by */
+     /*  do{ */
+     /*  if ( (Read(offset) & msk) == (value & msk) ) */
+     /*  break; */
+     /*  } while (not timeout); */
+
+#define PWR_CMD_DELAY                  0x03
+     /*  offset: the value to delay */
+     /*  msk: N/A */
+     /*  value: the unit of delay, 0: us, 1: ms */
+
+#define PWR_CMD_END                    0x04
+     /*  offset: N/A */
+     /*  msk: N/A */
+     /*  value: N/A */
+
+enum pwrseq_cmd_delat_unit {
+       PWRSEQ_DELAY_US,
+       PWRSEQ_DELAY_MS,
+};
+
+struct wl_pwr_cfg {
+       u16 offset;
+       u8 cmd:4;
+       u8 msk;
+       u8 value;
+};
+
+#define GET_PWR_CFG_OFFSET(__PWR_CMD)          __PWR_CMD.offset
+#define GET_PWR_CFG_CMD(__PWR_CMD)             __PWR_CMD.cmd
+#define GET_PWR_CFG_MASK(__PWR_CMD)            __PWR_CMD.msk
+#define GET_PWR_CFG_VALUE(__PWR_CMD)           __PWR_CMD.value
+
 static struct wl_pwr_cfg rtl8188E_power_on_flow[] = {
        { 0x0006, PWR_CMD_POLLING, BIT(1), BIT(1) },
        { 0x0002, PWR_CMD_WRITE, BIT(0) | BIT(1), 0 }, /* reset BB */

diff --git a/drivers/staging/r8188eu/include/HalPwrSeqCmd.h b/drivers/staging/r8188eu/include/HalPwrSeqCmd.h
index 869f54d99e572394139925a330b7f8848cbb4277..0886300d26bfb11fdad01024dab88227609fb600 100644 (file)
--- a/drivers/staging/r8188eu/include/HalPwrSeqCmd.h
+++ b/drivers/staging/r8188eu/include/HalPwrSeqCmd.h
@@ -6,53 +6,6 @@
 
 #include "drv_types.h"
 
-/*---------------------------------------------*/
-/* 3 The value of cmd: 4 bits */
-/*---------------------------------------------*/
-
-#define PWR_CMD_WRITE                  0x01
-     /*  offset: the read register offset */
-     /*  msk: the mask of the write bits */
-     /*  value: write value */
-     /*  note: driver shall implement this cmd by read & msk after write */
-
-#define PWR_CMD_POLLING                        0x02
-     /*  offset: the read register offset */
-     /*  msk: the mask of the polled value */
-     /*  value: the value to be polled, masked by the msd field. */
-     /*  note: driver shall implement this cmd by */
-     /*  do{ */
-     /*  if ( (Read(offset) & msk) == (value & msk) ) */
-     /*  break; */
-     /*  } while (not timeout); */
-
-#define PWR_CMD_DELAY                  0x03
-     /*  offset: the value to delay */
-     /*  msk: N/A */
-     /*  value: the unit of delay, 0: us, 1: ms */
-
-#define PWR_CMD_END                    0x04
-     /*  offset: N/A */
-     /*  msk: N/A */
-     /*  value: N/A */
-
-enum pwrseq_cmd_delat_unit {
-       PWRSEQ_DELAY_US,
-       PWRSEQ_DELAY_MS,
-};
-
-struct wl_pwr_cfg {
-       u16 offset;
-       u8 cmd:4;
-       u8 msk;
-       u8 value;
-};
-
-#define GET_PWR_CFG_OFFSET(__PWR_CMD)          __PWR_CMD.offset
-#define GET_PWR_CFG_CMD(__PWR_CMD)             __PWR_CMD.cmd
-#define GET_PWR_CFG_MASK(__PWR_CMD)            __PWR_CMD.msk
-#define GET_PWR_CFG_VALUE(__PWR_CMD)           __PWR_CMD.value
-
 enum r8188eu_pwr_seq {
        PWR_ON_FLOW,
        DISABLE_FLOW,