arm64: dts: freescale: add initial device tree for TQMLS1088A

This adds support for TQMLS1088A SOM on MBLS10xxA baseboard.

Signed-off-by: Gregor Herburger <gregor.herburger@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 62315da40c1700f2dfefc8f643f2eba7d7b1f627..300049037eb0bd56be54457f908dca527046626f 100644 (file)
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -23,6 +23,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-tqmls1046a-mbls10xxa.dtb
 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-qds.dtb
 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb
 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-ten64.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-tqmls1088a-mbls10xxa.dtb
 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb
 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2081a-rdb.dtb

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-tqmls1088a-mbls10xxa.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-tqmls1088a-mbls10xxa.dts
new file mode 100644 (file)
index 0000000..e567918
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-tqmls1088a-mbls10xxa.dts
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright (c) 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Gregor Herburger, Timo Herbrecher
+ *
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+#include "fsl-ls1088a-tqmls1088a.dtsi"
+#include "tqmls10xxa-mbls10xxa.dtsi"
+
+/ {
+       model = "TQ-Systems GmbH LS1088A TQMLS1088A SoM on MBLS10xxA board";
+       compatible = "tq,ls1088a-tqmls1088a-mbls10xxa", "tq,ls1088a-tqmls1088a",
+                    "fsl,ls1088a";
+
+       aliases {
+               dpmac1 = &dpmac1;
+               dpmac2 = &dpmac2;
+               dpmac3 = &dpmac3;
+               dpmac4 = &dpmac4;
+               dpmac5 = &dpmac5;
+               dpmac6 = &dpmac6;
+               dpmac7 = &dpmac7;
+               dpmac8 = &dpmac8;
+               dpmac9 = &dpmac9;
+               dpmac10 = &dpmac10;
+               qsgmii-s1-p1 = &qsgmii1_phy1;
+               qsgmii-s1-p2 = &qsgmii1_phy2;
+               qsgmii-s1-p3 = &qsgmii1_phy3;
+               qsgmii-s1-p4 = &qsgmii1_phy4;
+               qsgmii-s2-p1 = &qsgmii2_phy1;
+               qsgmii-s2-p2 = &qsgmii2_phy2;
+               qsgmii-s2-p3 = &qsgmii2_phy3;
+               qsgmii-s2-p4 = &qsgmii2_phy4;
+               rgmii-s1 = &rgmii_phy1;
+               rgmii-s2 = &rgmii_phy2;
+               serial0 = &duart0;
+               serial1 = &duart1;
+       };
+
+       chosen {
+               stdout-path = &duart1;
+       };
+};
+
+&esdhc {
+       cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
+       wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
+};
+
+&sfp1_i2c {
+       status = "okay";
+};
+
+&sfp2_i2c {
+       status = "okay";
+};
+
+#include "tqmls1088a-mbls10xxa-mc.dtsi"

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-tqmls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a-tqmls1088a.dtsi
new file mode 100644 (file)
index 0000000..9a0f214
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-tqmls1088a.dtsi
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright (c) 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Gregor Herburger, Timo Herbrecher
+ *
+ * Device Tree Include file for LS1088A based SoM of TQ
+ */
+
+#include "fsl-ls1088a.dtsi"
+#include "tqmls10xxa.dtsi"
+
+&qspi {
+       num-cs = <2>;
+       status = "okay";
+
+       qflash0: flash@0 {
+               compatible = "jedec,spi-nor";
+               reg = <0>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               spi-max-frequency = <62500000>;
+               spi-rx-bus-width = <4>;
+               spi-tx-bus-width = <4>;
+
+               partitions {
+                       compatible = "fixed-partitions";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+               };
+       };
+
+       qflash1: flash@1 {
+               compatible = "jedec,spi-nor";
+               reg = <1>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               spi-max-frequency = <62500000>;
+               spi-rx-bus-width = <4>;
+               spi-tx-bus-width = <4>;
+       };
+};

diff --git a/arch/arm64/boot/dts/freescale/tqmls1088a-mbls10xxa-mc.dtsi b/arch/arm64/boot/dts/freescale/tqmls1088a-mbls10xxa-mc.dtsi
new file mode 100644 (file)
index 0000000..2471bb1
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/tqmls1088a-mbls10xxa-mc.dtsi
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright (c) 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Gregor Herburger, Timo Herbrecher
+ *
+ * Device Tree Include file for MBLS10xxA from TQ (MC related sections)
+ */
+
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+       sfp1: sfp1 {
+               compatible = "sff,sfp";
+               i2c-bus = <&sfp1_i2c>;
+               mod-def0-gpios = <&gpioexp2 2 GPIO_ACTIVE_LOW>;
+               los-gpios = <&gpioexp2 3 GPIO_ACTIVE_HIGH>;
+               tx-fault-gpios = <&gpioexp2 0 GPIO_ACTIVE_HIGH>;
+               tx-disable-gpios = <&gpioexp2 1 GPIO_ACTIVE_HIGH>;
+       };
+
+       sfp2: sfp2 {
+               compatible = "sff,sfp";
+               i2c-bus = <&sfp2_i2c>;
+               mod-def0-gpios = <&gpioexp2 10 GPIO_ACTIVE_LOW>;
+               los-gpios = <&gpioexp2 11 GPIO_ACTIVE_HIGH>;
+               tx-fault-gpios = <&gpioexp2 8 GPIO_ACTIVE_HIGH>;
+               tx-disable-gpios = <&gpioexp2 9 GPIO_ACTIVE_HIGH>;
+       };
+};
+
+&dpmac1 {
+       pcs-handle = <&pcs1>;
+};
+
+&dpmac2 {
+       pcs-handle = <&pcs2>;
+};
+
+&dpmac3 {
+       pcs-handle = <&pcs3_0>;
+};
+
+&dpmac4 {
+       pcs-handle = <&pcs3_1>;
+};
+
+&dpmac5 {
+       pcs-handle = <&pcs3_2>;
+};
+
+&dpmac6 {
+       pcs-handle = <&pcs3_3>;
+};
+
+&dpmac7 {
+       pcs-handle = <&pcs7_0>;
+};
+
+&dpmac8 {
+       pcs-handle = <&pcs7_1>;
+};
+
+&dpmac9 {
+       pcs-handle = <&pcs7_2>;
+};
+
+&dpmac10 {
+       pcs-handle = <&pcs7_3>;
+};
+
+&emdio1 {
+       status = "okay";
+
+       qsgmii2_phy1: ethernet-phy@0 {
+               compatible = "ethernet-phy-ieee802.3-c22";
+               reg = <0x00>;
+       };
+
+       qsgmii2_phy2: ethernet-phy@1 {
+               compatible = "ethernet-phy-ieee802.3-c22";
+               reg = <0x01>;
+       };
+
+       qsgmii2_phy3: ethernet-phy@2 {
+               compatible = "ethernet-phy-ieee802.3-c22";
+               reg = <0x02>;
+       };
+
+       qsgmii2_phy4: ethernet-phy@3 {
+               compatible = "ethernet-phy-ieee802.3-c22";
+               reg = <0x03>;
+       };
+
+       rgmii_phy2: ethernet-phy@c {
+               compatible = "ethernet-phy-ieee802.3-c22";
+               reg = <0x0c>;
+               ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
+               ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
+               ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
+       };
+
+       rgmii_phy1: ethernet-phy@e {
+               compatible = "ethernet-phy-ieee802.3-c22";
+               reg = <0x0e>;
+               ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
+               ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
+               ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
+       };
+
+       qsgmii1_phy1: ethernet-phy@1c {
+               compatible = "ethernet-phy-ieee802.3-c22";
+               reg = <0x1c>;
+       };
+
+       qsgmii1_phy2: ethernet-phy@1d {
+               compatible = "ethernet-phy-ieee802.3-c22";
+               reg = <0x1d>;
+       };
+
+       qsgmii1_phy3: ethernet-phy@1e {
+               compatible = "ethernet-phy-ieee802.3-c22";
+               reg = <0x1e>;
+       };
+
+       qsgmii1_phy4: ethernet-phy@1f {
+               compatible = "ethernet-phy-ieee802.3-c22";
+               reg = <0x1f>;
+       };
+};
+
+&pcs_mdio1 {
+       status = "okay";
+};
+
+&pcs_mdio2 {
+       status = "okay";
+};
+
+&pcs_mdio3 {
+       status = "okay";
+};
+
+&pcs_mdio7 {
+       status = "okay";
+};