phy: qcom-qmp-ufs: Add HS G4 mode support to SM8250 SoC

UFS PHY in SM8250 SoC is capable of operating at HS G4 mode. Hence, add the
required register settings using the tables_hs_g4 struct instance. This
also requires a separate qmp_phy_cfg for SM8250 instead of reusing SM8150.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20230114071009.88102-9-manivannan.sadhasivam@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h
index 43255e8bf03837facbb712cc87b342074ea916e1..07959964fcf6bebb5ea0d607b80bda8272825597 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h
@@ -16,6 +16,7 @@
 #define QPHY_V5_PCS_UFS_PLL_CNTL                       0x02c
 #define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL           0x030
 #define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL           0x038
+#define QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL            0x060
 #define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY           0x074
 #define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY           0x0b4
 #define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL               0x124

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index 57d0744d18c27d4c4b15386f1555b7622f35cbe0..152b1b367df38aa11382d19896c69d7ba5171387 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -454,6 +454,34 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_pcs[] = {
        QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a),
 };
 
+static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_tx[] = {
+       QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xe5),
+};
+
+static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_rx[] = {
+       QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
+       QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81),
+       QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
+       QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f),
+       QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
+       QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00),
+       QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x09),
+       QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
+       QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
+       QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20),
+       QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80),
+       QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
+       QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
+       QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
+       QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
+       QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
+       QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x2c),
+       QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d),
+       QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d),
+       QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed),
+       QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c),
+};
+
 static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] = {
        QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
        QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
@@ -812,6 +840,38 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
        .regs                   = ufsphy_v4_regs_layout,
 };
 
+static const struct qmp_phy_cfg sm8250_ufsphy_cfg = {
+       .lanes                  = 2,
+
+       .tbls = {
+               .serdes         = sm8150_ufsphy_serdes,
+               .serdes_num     = ARRAY_SIZE(sm8150_ufsphy_serdes),
+               .tx             = sm8150_ufsphy_tx,
+               .tx_num         = ARRAY_SIZE(sm8150_ufsphy_tx),
+               .rx             = sm8150_ufsphy_rx,
+               .rx_num         = ARRAY_SIZE(sm8150_ufsphy_rx),
+               .pcs            = sm8150_ufsphy_pcs,
+               .pcs_num        = ARRAY_SIZE(sm8150_ufsphy_pcs),
+       },
+       .tbls_hs_b = {
+               .serdes         = sm8150_ufsphy_hs_b_serdes,
+               .serdes_num     = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
+       },
+       .tbls_hs_g4 = {
+               .tx             = sm8250_ufsphy_hs_g4_tx,
+               .tx_num         = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx),
+               .rx             = sm8250_ufsphy_hs_g4_rx,
+               .rx_num         = ARRAY_SIZE(sm8250_ufsphy_hs_g4_rx),
+               .pcs            = sm8150_ufsphy_hs_g4_pcs,
+               .pcs_num        = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
+       },
+       .clk_list               = sdm845_ufs_phy_clk_l,
+       .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
+       .vreg_list              = qmp_phy_vreg_l,
+       .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
+       .regs                   = ufsphy_v4_regs_layout,
+};
+
 static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
        .lanes                  = 2,
 
@@ -1364,7 +1424,7 @@ static const struct of_device_id qmp_ufs_of_match_table[] = {
                .data = &sm8150_ufsphy_cfg,
        }, {
                .compatible = "qcom,sm8250-qmp-ufs-phy",
-               .data = &sm8150_ufsphy_cfg,
+               .data = &sm8250_ufsphy_cfg,
        }, {
                .compatible = "qcom,sm8350-qmp-ufs-phy",
                .data = &sm8350_ufsphy_cfg,