crypto: hisilicon/sec - not need to enable sm4 extra mode at HW V3

[ Upstream commit f8a2652826444d13181061840b96a5d975d5b6c6 ]

It is not need to enable sm4 extra mode in at HW V3. Here is fix it.

Signed-off-by: Kai Ye <yekai13@huawei.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/crypto/hisilicon/sec2/sec_main.c b/drivers/crypto/hisilicon/sec2/sec_main.c
index 90551bf38b523a3e3f67974c93a4a855e73de7d5..03d239cfdf8c62fab22b7f996f2a53e76f95404d 100644 (file)
--- a/drivers/crypto/hisilicon/sec2/sec_main.c
+++ b/drivers/crypto/hisilicon/sec2/sec_main.c
@@ -443,9 +443,11 @@ static int sec_engine_init(struct hisi_qm *qm)
 
        writel(SEC_SAA_ENABLE, qm->io_base + SEC_SAA_EN_REG);
 
-       /* Enable sm4 extra mode, as ctr/ecb */
-       writel_relaxed(SEC_BD_ERR_CHK_EN0,
-                      qm->io_base + SEC_BD_ERR_CHK_EN_REG0);
+       /* HW V2 enable sm4 extra mode, as ctr/ecb */
+       if (qm->ver < QM_HW_V3)
+               writel_relaxed(SEC_BD_ERR_CHK_EN0,
+                              qm->io_base + SEC_BD_ERR_CHK_EN_REG0);
+
        /* Enable sm4 xts mode multiple iv */
        writel_relaxed(SEC_BD_ERR_CHK_EN1,
                       qm->io_base + SEC_BD_ERR_CHK_EN_REG1);