u64 val;
addr += idx;
- if ((idx == KP_SPI_REG_CONFIG) && (cs->conf_cache >= 0)) {
+ if ((idx == KP_SPI_REG_CONFIG) && (cs->conf_cache >= 0))
return cs->conf_cache;
- }
+
val = readq(addr);
return val;
}
timeout = jiffies + msecs_to_jiffies(1000);
while (!(kp_spi_read_reg(cs, idx) & bit)) {
if (time_after(jiffies, timeout)) {
- if (!(kp_spi_read_reg(cs, idx) & bit)) {
+ if (!(kp_spi_read_reg(cs, idx) & bit))
return -ETIMEDOUT;
- } else {
+ else
return 0;
- }
}
cpu_relax();
}
cs = spidev->controller_state;
if (!cs) {
cs = kzalloc(sizeof(*cs), GFP_KERNEL);
- if (!cs) {
+ if (!cs)
return -ENOMEM;
- }
cs->base = kpspi->base;
cs->conf_cache = -1;
spidev->controller_state = cs;
cs = spidev->controller_state;
/* reject invalid messages and transfers */
- if (list_empty(&m->transfers)) {
+ if (list_empty(&m->transfers))
return -EINVAL;
- }
/* validate input */
list_for_each_entry(transfer, &m->transfers, transfer_list) {
sc.reg = kp_spi_read_reg(cs, KP_SPI_REG_CONFIG);
/* ...direction */
- if (transfer->tx_buf) {
+ if (transfer->tx_buf)
sc.bitfield.trm = KP_SPI_REG_CONFIG_TRM_TX;
- }
- else if (transfer->rx_buf) {
+ else if (transfer->rx_buf)
sc.bitfield.trm = KP_SPI_REG_CONFIG_TRM_RX;
- }
/* ...word length */
- if (transfer->bits_per_word) {
+ if (transfer->bits_per_word)
word_len = transfer->bits_per_word;
- }
sc.bitfield.wl = word_len - 1;
/* ...chip select */
}
}
- if (transfer->delay_usecs) {
+ if (transfer->delay_usecs)
udelay(transfer->delay_usecs);
- }
}
/* de-assert chip select to end the sequence */
{
struct kp_spi_controller_state *cs = spidev->controller_state;
- if (cs) {
+ if (cs)
kfree(cs);
- }
}
/******************
kpspi->dev = &pldev->dev;
master->num_chipselect = 4;
- if (pldev->id != -1) {
+ if (pldev->id != -1)
master->bus_num = pldev->id;
- }
r = platform_get_resource(pldev, IORESOURCE_MEM, 0);
if (r == NULL) {