arm64: dts: renesas: r9a08g045: Add nodes for SDHI1 and SDHI2

Add DT nodes for SDHI1 and SDHI2 available on RZ/G3S (R9A08G045).

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20231010132701.1658737-4-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
index 7971e44a5a0ac88b3c097ab4c1701dc85f335477..534b728a8e14b927b064c66eddc602f06f6b21d3 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
@@ -118,6 +118,36 @@
                        status = "disabled";
                };
 
+               sdhi1: mmc@11c10000 {
+                       compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi";
+                       reg = <0x0 0x11c10000 0 0x10000>;
+                       interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK>,
+                                <&cpg CPG_MOD R9A08G045_SDHI1_CLK_HS>,
+                                <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK2>,
+                                <&cpg CPG_MOD R9A08G045_SDHI1_ACLK>;
+                       clock-names = "core", "clkh", "cd", "aclk";
+                       resets = <&cpg R9A08G045_SDHI1_IXRST>;
+                       power-domains = <&cpg>;
+                       status = "disabled";
+               };
+
+               sdhi2: mmc@11c20000 {
+                       compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi";
+                       reg = <0x0 0x11c20000 0 0x10000>;
+                       interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK>,
+                                <&cpg CPG_MOD R9A08G045_SDHI2_CLK_HS>,
+                                <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK2>,
+                                <&cpg CPG_MOD R9A08G045_SDHI2_ACLK>;
+                       clock-names = "core", "clkh", "cd", "aclk";
+                       resets = <&cpg R9A08G045_SDHI2_IXRST>;
+                       power-domains = <&cpg>;
+                       status = "disabled";
+               };
+
                gic: interrupt-controller@12400000 {
                        compatible = "arm,gic-v3";
                        #interrupt-cells = <3>;