intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
 
-       dev_priv->display.fdi_link_train(crtc, crtc_state);
+       hsw_fdi_link_train(encoder, crtc_state);
 
        intel_ddi_enable_pipe_clock(crtc_state);
 }
 
  * DDI A (which is used for eDP)
  */
 
-void hsw_fdi_link_train(struct intel_crtc *crtc,
+void hsw_fdi_link_train(struct intel_encoder *encoder,
                        const struct intel_crtc_state *crtc_state)
 {
-       struct drm_device *dev = crtc->base.dev;
-       struct drm_i915_private *dev_priv = to_i915(dev);
-       struct intel_encoder *encoder;
+       struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+       struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        u32 temp, i, rx_ctl_val, ddi_pll_sel;
 
-       for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
-               WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
-               intel_prepare_dp_ddi_buffers(encoder, crtc_state);
-       }
+       intel_prepare_dp_ddi_buffers(encoder, crtc_state);
 
        /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
         * mode set "sequence for CRT port" document:
 
 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
                                const struct intel_crtc_state *old_crtc_state,
                                const struct drm_connector_state *old_conn_state);
-void hsw_fdi_link_train(struct intel_crtc *crtc,
+void hsw_fdi_link_train(struct intel_encoder *encoder,
                        const struct intel_crtc_state *crtc_state);
 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
 
        } else if (IS_IVYBRIDGE(dev_priv)) {
                /* FIXME: detect B0+ stepping and use auto training */
                dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
-       } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
-               dev_priv->display.fdi_link_train = hsw_fdi_link_train;
        }
 
        if (INTEL_GEN(dev_priv) >= 9)