drm/xe/arl: Add Arrow Lake H support

ARL-H uses the same media and display IP as MTL, and a version 12.74
graphics IP (referred to as Xe_LPG+). From a driver point of view, we
should be able to just treat the whole platform as MTL and rely on
GRAPHICS_VERx100 checks to handle any spots where ARL's Xe_LPG+ needs
different handling from MTL's Xe_LPG (i.e., workarounds).

v2: Resolve conflict and Reorder PCI ids in sorted order
v3: Append signed-off-by commiter to this commit

Bspec: 55420
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240229070806.3402641-4-dnyaneshwar.bhadane@intel.com

diff --git a/include/drm/xe_pciids.h b/include/drm/xe_pciids.h
index de1a344737bc90b9aad1e816afbdc7f654b16ea1..bc7cbef6e9d8a500e591e7f04c13d72bdf81f3f6 100644 (file)
--- a/include/drm/xe_pciids.h
+++ b/include/drm/xe_pciids.h
@@ -176,10 +176,13 @@
 /* MTL / ARL */
 #define XE_MTL_IDS(MACRO__, ...)               \
        MACRO__(0x7D40, ## __VA_ARGS__),        \
+       MACRO__(0x7D41, ## __VA_ARGS__),        \
        MACRO__(0x7D45, ## __VA_ARGS__),        \
+       MACRO__(0x7D51, ## __VA_ARGS__),        \
        MACRO__(0x7D55, ## __VA_ARGS__),        \
        MACRO__(0x7D60, ## __VA_ARGS__),        \
        MACRO__(0x7D67, ## __VA_ARGS__),        \
+       MACRO__(0x7DD1, ## __VA_ARGS__),        \
        MACRO__(0x7DD5, ## __VA_ARGS__)
 
 #define XE_LNL_IDS(MACRO__, ...) \