drm/msm/a6xx: Improve GMU force shutdown sequence

The GMU force shutdown sequence involves some additional register cleanup
which was not implemented previously. Do so.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/543340/
Signed-off-by: Rob Clark <robdclark@chromium.org>

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 452beb90d53cca45860ef36e26af741a64b50d84..0bf12524cae423db7799aed03d3278473943827a 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -899,6 +899,13 @@ static void a6xx_gmu_force_off(struct a6xx_gmu *gmu)
        /* Make sure there are no outstanding RPMh votes */
        a6xx_gmu_rpmh_off(gmu);
 
+       /* Clear the WRITEDROPPED fields and put fence into allow mode */
+       gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS_CLR, 0x7);
+       gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);
+
+       /* Make sure the above writes go through */
+       wmb();
+
        /* Halt the gmu cm3 core */
        gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1);