drm/amdgpu: add hdp clock gating for Arcturus

Add hdp CGLS for Arcturus in set common clockgating function

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 0379f4290ea15f33d622a64c2107a382e84b4732..258cbaafb5353217bf4f0267cae16f967f079718 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -1259,7 +1259,8 @@ static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable
 {
        uint32_t def, data;
 
-       if (adev->asic_type == CHIP_VEGA20) {
+       if (adev->asic_type == CHIP_VEGA20 ||
+               adev->asic_type == CHIP_ARCTURUS) {
                def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
 
                if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
@@ -1391,6 +1392,10 @@ static int soc15_common_set_clockgating_state(void *handle,
                soc15_update_rom_medium_grain_clock_gating(adev,
                                state == AMD_CG_STATE_GATE ? true : false);
                break;
+       case CHIP_ARCTURUS:
+               soc15_update_hdp_light_sleep(adev,
+                               state == AMD_CG_STATE_GATE ? true : false);
+               break;
        default:
                break;
        }