iio: adc: meson: init channels 0,1 input muxes

Set up input channels 0,1 muxes in the same way as for the channels 2-7
later in the code.

Signed-off-by: George Stark <gnstark@sberdevices.ru>
Link: https://lore.kernel.org/r/20230715110654.6035-2-gnstark@sberdevices.ru
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
index 81659c0abf6c6c3de21af631a9084dabe75835a7..650ab9390514835ccaf669e360f60a1a856488b9 100644 (file)
--- a/drivers/iio/adc/meson_saradc.c
+++ b/drivers/iio/adc/meson_saradc.c
@@ -899,6 +899,22 @@ static int meson_sar_adc_init(struct iio_dev *indio_dev)
                           MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK,
                           regval);
 
+       regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
+                          MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW,
+                          MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW);
+
+       regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
+                          MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW,
+                          MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW);
+
+       regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
+                          MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW,
+                          MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW);
+
+       regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
+                          MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW,
+                          MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW);
+
        /*
         * set up the input channel muxes in MESON_SAR_ADC_AUX_SW
         * (2 = SAR_ADC_CH2, 3 = SAR_ADC_CH3, ...) and enable