clk: imx: imx93: Add nic and A55 clk

The A55 clock logic as below:
     A55_PLL ----------------->\
                                A55_SEL-->A55_CORE
     A55_CCM_ROOT--->A55_GATE->/

Add A55 CPU clk to support freq change.
Add NIC CLK to reflect the clk status

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20230403095300.3386988-8-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

diff --git a/drivers/clk/imx/clk-imx93.c b/drivers/clk/imx/clk-imx93.c
index de1ed1d8ba541a5176737aa46efdb03f3482104b..07b4a043e44952e550d4c869cc2834374d2985f1 100644 (file)
--- a/drivers/clk/imx/clk-imx93.c
+++ b/drivers/clk/imx/clk-imx93.c
@@ -33,6 +33,7 @@ static u32 share_count_sai2;
 static u32 share_count_sai3;
 static u32 share_count_mub;
 
+static const char * const a55_core_sels[] = {"a55_alt", "arm_pll"};
 static const char *parent_names[MAX_SEL][4] = {
        {"osc_24m", "sys_pll_pfd0_div2", "sys_pll_pfd1_div2", "video_pll"},
        {"osc_24m", "sys_pll_pfd0_div2", "sys_pll_pfd1_div2", "sys_pll_pfd2_div2"},
@@ -55,7 +56,7 @@ static const struct imx93_clk_root {
        /* a55/m33/bus critical clk for system run */
        { IMX93_CLK_A55_PERIPH,         "a55_periph_root",      0x0000, FAST_SEL, CLK_IS_CRITICAL },
        { IMX93_CLK_A55_MTR_BUS,        "a55_mtr_bus_root",     0x0080, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
-       { IMX93_CLK_A55,                "a55_root",             0x0100, FAST_SEL, CLK_IS_CRITICAL },
+       { IMX93_CLK_A55,                "a55_alt_root",         0x0100, FAST_SEL, CLK_IS_CRITICAL },
        { IMX93_CLK_M33,                "m33_root",             0x0180, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
        { IMX93_CLK_BUS_WAKEUP,         "bus_wakeup_root",      0x0280, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
        { IMX93_CLK_BUS_AON,            "bus_aon_root",         0x0300, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
@@ -117,6 +118,7 @@ static const struct imx93_clk_root {
        { IMX93_CLK_HSIO_USB_TEST_60M,  "hsio_usb_test_60m_root", 0x1f00, LOW_SPEED_IO_SEL, },
        { IMX93_CLK_HSIO_ACSCAN_80M,    "hsio_acscan_80m_root", 0x1f80, LOW_SPEED_IO_SEL, },
        { IMX93_CLK_HSIO_ACSCAN_480M,   "hsio_acscan_480m_root", 0x2000, MISC_SEL, },
+       { IMX93_CLK_NIC_AXI,            "nic_axi_root",         0x2080, FAST_SEL, CLK_IS_CRITICAL, },
        { IMX93_CLK_ML_APB,             "ml_apb_root",          0x2180, LOW_SPEED_IO_SEL, },
        { IMX93_CLK_ML,                 "ml_root",              0x2200, FAST_SEL, },
        { IMX93_CLK_MEDIA_AXI,          "media_axi_root",       0x2280, FAST_SEL, },
@@ -153,7 +155,7 @@ static const struct imx93_clk_ccgr {
        unsigned long flags;
        u32 *shared_count;
 } ccgr_array[] = {
-       { IMX93_CLK_A55_GATE,           "a55",          "a55_root",             0x8000, },
+       { IMX93_CLK_A55_GATE,           "a55_alt",      "a55_alt_root",         0x8000, },
        /* M33 critical clk for system run */
        { IMX93_CLK_CM33_GATE,          "cm33",         "m33_root",             0x8040, CLK_IS_CRITICAL },
        { IMX93_CLK_ADC1_GATE,          "adc1",         "adc_root",             0x82c0, },
@@ -291,6 +293,9 @@ static int imx93_clocks_probe(struct platform_device *pdev)
        if (WARN_ON(!anatop_base))
                return -ENOMEM;
 
+       clks[IMX93_CLK_ARM_PLL] = imx_clk_fracn_gppll_integer("arm_pll", "osc_24m",
+                                                             anatop_base + 0x1000,
+                                                             &imx_fracn_gppll_integer);
        clks[IMX93_CLK_AUDIO_PLL] = imx_clk_fracn_gppll("audio_pll", "osc_24m", anatop_base + 0x1200,
                                                        &imx_fracn_gppll);
        clks[IMX93_CLK_VIDEO_PLL] = imx_clk_fracn_gppll("video_pll", "osc_24m", anatop_base + 0x1400,
@@ -318,6 +323,14 @@ static int imx93_clocks_probe(struct platform_device *pdev)
                                                 ccgr->shared_count);
        }
 
+       clks[IMX93_CLK_A55_SEL] = imx_clk_hw_mux2("a55_sel", base + 0x4820, 0, 1, a55_core_sels,
+                                                 ARRAY_SIZE(a55_core_sels));
+       clks[IMX93_CLK_A55_CORE] = imx_clk_hw_cpu("a55_core", "a55_sel",
+                                                 clks[IMX93_CLK_A55_SEL]->clk,
+                                                 clks[IMX93_CLK_A55_SEL]->clk,
+                                                 clks[IMX93_CLK_ARM_PLL]->clk,
+                                                 clks[IMX93_CLK_A55_GATE]->clk);
+
        imx_check_clk_hws(clks, IMX93_CLK_END);
 
        ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);