drm/i915: Make GT workaround upper bounds exclusive

Workarounds are documented in the bspec with an exclusive upper bound
(i.e., a "fixed" stepping that no longer needs the workaround).  This
makes our driver's use of an inclusive upper bound for stepping ranges
confusing; the differing notation between code and bspec makes it very
easy for mistakes to creep in.

Let's switch the upper bound of our IS_{GT,DISP}_STEP macros over to use
an exclusive upper bound like the bspec does.  This also has the benefit
of helping make sure workarounds are properly handled for new minor
steppings that show up (e.g., an A1 between the A0 and B0 we already
knew about) --- if the new intermediate stepping pulls in hardware fixes
early, there will be an update to the workaround definition which lets
us know we need to change our code.  If the new stepping does not pull a
hardware fix earlier, then the new stepping will already be captured
properly by the "[begin, fix)" range in the code.

We'll probably need to be extra vigilant in code review of new
workarounds for the near future to make sure developers notice the new
semantics of workaround bounds.  But we just migrated a bunch of our
platforms from the IS_REVID bounds over to IS_{GT,DISP}_STEP, so people
are already adjusting to the new macros and now is a good time to make
this change too.

[mattrope: Split out GT changes to apply through gt-next tree]
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210717051426.4120328-8-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 87b06572fd2e2cf083d4ebdd54f8fed0fff6e5d9..a69f5c438c7263cbf860dc8fb1d504b23b472d26 100644 (file)
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -42,7 +42,7 @@ int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode)
                        vf_flush_wa = true;
 
                /* WaForGAMHang:kbl */
-               if (IS_KBL_GT_STEP(rq->engine->i915, 0, STEP_B0))
+               if (IS_KBL_GT_STEP(rq->engine->i915, 0, STEP_C0))
                        dc_flush_wa = true;
        }
 

diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index 50d11a84e7a9c201b63b2f7829a21ff2b6669811..e3a2a2fa5f9488b368ee7ba5115583da57292776 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -157,7 +157,7 @@ intel_gt_setup_fake_lmem(struct intel_gt *gt)
 static bool get_legacy_lowmem_region(struct intel_uncore *uncore,
                                     u64 *start, u32 *size)
 {
-       if (!IS_DG1_GT_STEP(uncore->i915, STEP_A0, STEP_B0))
+       if (!IS_DG1_GT_STEP(uncore->i915, STEP_A0, STEP_C0))
                return false;
 
        *start = 0;

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 685c6115d380275d51947547d77b7baa4462966d..247f0331ebee39f0d87ee8684526b9c7cd28fb37 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -838,7 +838,7 @@ skl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
                    GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
 
        /* WaInPlaceDecompressionHang:skl */
-       if (IS_SKL_GT_STEP(i915, STEP_A0, STEP_H0 - 1))
+       if (IS_SKL_GT_STEP(i915, STEP_A0, STEP_H0))
                wa_write_or(wal,
                            GEN9_GAMT_ECO_REG_RW_IA,
                            GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
@@ -850,7 +850,7 @@ kbl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
        gen9_gt_workarounds_init(i915, wal);
 
        /* WaDisableDynamicCreditSharing:kbl */
-       if (IS_KBL_GT_STEP(i915, 0, STEP_B0))
+       if (IS_KBL_GT_STEP(i915, 0, STEP_C0))
                wa_write_or(wal,
                            GAMT_CHKN_BIT_REG,
                            GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING);
@@ -961,7 +961,7 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 
        /* Wa_1607087056:icl,ehl,jsl */
        if (IS_ICELAKE(i915) ||
-           IS_JSL_EHL_GT_STEP(i915, STEP_A0, STEP_A0))
+           IS_JSL_EHL_GT_STEP(i915, STEP_A0, STEP_B0))
                wa_write_or(wal,
                            SLICE_UNIT_LEVEL_CLKGATE,
                            L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
@@ -1015,19 +1015,19 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
        gen12_gt_workarounds_init(i915, wal);
 
        /* Wa_1409420604:tgl */
-       if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0))
+       if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_B0))
                wa_write_or(wal,
                            SUBSLICE_UNIT_LEVEL_CLKGATE2,
                            CPSSUNIT_CLKGATE_DIS);
 
        /* Wa_1607087056:tgl also know as BUG:1409180338 */
-       if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0))
+       if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_B0))
                wa_write_or(wal,
                            SLICE_UNIT_LEVEL_CLKGATE,
                            L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
 
        /* Wa_1408615072:tgl[a0] */
-       if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0))
+       if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_B0))
                wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
                            VSUNIT_CLKGATE_DIS_TGL);
 }
@@ -1038,7 +1038,7 @@ dg1_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
        gen12_gt_workarounds_init(i915, wal);
 
        /* Wa_1607087056:dg1 */
-       if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0))
+       if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_B0))
                wa_write_or(wal,
                            SLICE_UNIT_LEVEL_CLKGATE,
                            L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
@@ -1436,7 +1436,7 @@ static void dg1_whitelist_build(struct intel_engine_cs *engine)
        tgl_whitelist_build(engine);
 
        /* GEN:BUG:1409280441:dg1 */
-       if (IS_DG1_GT_STEP(engine->i915, STEP_A0, STEP_A0) &&
+       if (IS_DG1_GT_STEP(engine->i915, STEP_A0, STEP_B0) &&
            (engine->class == RENDER_CLASS ||
             engine->class == COPY_ENGINE_CLASS))
                whitelist_reg_ext(w, RING_ID(engine->mmio_base),
@@ -1504,8 +1504,8 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 {
        struct drm_i915_private *i915 = engine->i915;
 
-       if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0) ||
-           IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0)) {
+       if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_B0) ||
+           IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_B0)) {
                /*
                 * Wa_1607138336:tgl[a0],dg1[a0]
                 * Wa_1607063988:tgl[a0],dg1[a0]
@@ -1515,7 +1515,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
                            GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
        }
 
-       if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0)) {
+       if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_B0)) {
                /*
                 * Wa_1606679103:tgl
                 * (see also Wa_1606682166:icl)
@@ -1550,7 +1550,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
        }
 
        if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) ||
-           IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0) ||
+           IS_DG1_GT_STEP(i915, STEP_A0, STEP_B0) ||
            IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
                /* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */
                wa_masked_en(wal, GEN7_ROW_CHICKEN2,
@@ -1564,7 +1564,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
        }
 
 
-       if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0) ||
+       if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_B0) ||
            IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
                /*
                 * Wa_1607030317:tgl
@@ -1925,7 +1925,7 @@ xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
        struct drm_i915_private *i915 = engine->i915;
 
        /* WaKBLVECSSemaphoreWaitPoll:kbl */
-       if (IS_KBL_GT_STEP(i915, STEP_A0, STEP_E0)) {
+       if (IS_KBL_GT_STEP(i915, STEP_A0, STEP_F0)) {
                wa_write(wal,
                         RING_SEMA_WAIT_POLL(engine->mmio_base),
                         1);

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d0027b0e8afc4b0f73fe1c698da5735a29422020..3ee350129f3635835800660129f67a0b577afb24 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1339,7 +1339,7 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
 
 #define IS_GT_STEP(__i915, since, until) \
        (drm_WARN_ON(&(__i915)->drm, INTEL_GT_STEP(__i915) == STEP_NONE), \
-        INTEL_GT_STEP(__i915) >= (since) && INTEL_GT_STEP(__i915) <= (until))
+        INTEL_GT_STEP(__i915) >= (since) && INTEL_GT_STEP(__i915) < (until))
 
 static __always_inline unsigned int
 __platform_mask_index(const struct intel_runtime_info *info,

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 839ab94b36fe08934754cb8bfaf2b1c4b4e3594f..0e5d8a88f537d67abffa9616f6a2e069e41a301e 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7377,7 +7377,7 @@ static void dg1_init_clock_gating(struct drm_i915_private *dev_priv)
        gen12lp_init_clock_gating(dev_priv);
 
        /* Wa_1409836686:dg1[a0] */
-       if (IS_DG1_GT_STEP(dev_priv, STEP_A0, STEP_A0))
+       if (IS_DG1_GT_STEP(dev_priv, STEP_A0, STEP_B0))
                intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
                           DPT_GATING_DIS);
 }
@@ -7462,12 +7462,12 @@ static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
                   FBC_LLC_FULLY_OPEN);
 
        /* WaDisableSDEUnitClockGating:kbl */
-       if (IS_KBL_GT_STEP(dev_priv, 0, STEP_B0))
+       if (IS_KBL_GT_STEP(dev_priv, 0, STEP_C0))
                intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGCTL6) |
                           GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
 
        /* WaDisableGamClockGating:kbl */
-       if (IS_KBL_GT_STEP(dev_priv, 0, STEP_B0))
+       if (IS_KBL_GT_STEP(dev_priv, 0, STEP_C0))
                intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL1, intel_uncore_read(&dev_priv->uncore, GEN6_UCGCTL1) |
                           GEN6_GAMUNIT_CLOCK_GATE_DISABLE);