int kvm_cpu_has_interrupt(struct kvm_vcpu *v);
 void kvm_pic_update_irq(struct kvm_pic *s);
 
-#define IOAPIC_NUM_PINS  24
+#define IOAPIC_NUM_PINS  KVM_IOAPIC_NUM_PINS
 #define IOAPIC_VERSION_ID 0x11 /* IOAPIC version */
 #define IOAPIC_EDGE_TRIG  0
 #define IOAPIC_LEVEL_TRIG 1
 
                        &pic_irqchip(kvm)->pics[1],
                        sizeof(struct kvm_pic_state));
                break;
+       case KVM_IRQCHIP_IOAPIC:
+               memcpy (&chip->chip.ioapic,
+                       ioapic_irqchip(kvm),
+                       sizeof(struct kvm_ioapic_state));
+               break;
        default:
                r = -EINVAL;
                break;
                        &chip->chip.pic,
                        sizeof(struct kvm_pic_state));
                break;
+       case KVM_IRQCHIP_IOAPIC:
+               memcpy (ioapic_irqchip(kvm),
+                       &chip->chip.ioapic,
+                       sizeof(struct kvm_ioapic_state));
+               break;
        default:
                r = -EINVAL;
                break;
 
        __u32 level;
 };
 
-/* for KVM_GET_IRQCHIP / KVM_SET_IRQCHIP */
+/* for KVM_GET_IRQCHIP and KVM_SET_IRQCHIP */
 struct kvm_pic_state {
        __u8 last_irr;  /* edge detection */
        __u8 irr;               /* interrupt request register */
        __u8 elcr_mask;
 };
 
+#define KVM_IOAPIC_NUM_PINS  24
+struct kvm_ioapic_state {
+       __u64 base_address;
+       __u32 ioregsel;
+       __u32 id;
+       __u32 irr;
+       __u32 pad;
+       union {
+               __u64 bits;
+               struct {
+                       __u8 vector;
+                       __u8 delivery_mode:3;
+                       __u8 dest_mode:1;
+                       __u8 delivery_status:1;
+                       __u8 polarity:1;
+                       __u8 remote_irr:1;
+                       __u8 trig_mode:1;
+                       __u8 mask:1;
+                       __u8 reserve:7;
+                       __u8 reserved[4];
+                       __u8 dest_id;
+               } fields;
+       } redirtbl[KVM_IOAPIC_NUM_PINS];
+};
+
 enum kvm_irqchip_id {
        KVM_IRQCHIP_PIC_MASTER   = 0,
        KVM_IRQCHIP_PIC_SLAVE    = 1,
+       KVM_IRQCHIP_IOAPIC       = 2,
 };
 
 struct kvm_irqchip {
         union {
                char dummy[512];  /* reserving space */
                struct kvm_pic_state pic;
+               struct kvm_ioapic_state ioapic;
        } chip;
 };