WREG32_SDMA(i, mmSDMA0_CNTL, temp);
 
                if (!amdgpu_sriov_vf(adev)) {
-                       ring = &adev->sdma.instance[i].ring;
-                       adev->nbio.funcs->sdma_doorbell_range(adev, i,
-                               ring->use_doorbell, ring->doorbell_index,
-                               adev->doorbell_index.sdma_doorbell_range);
-
                        /* unhalt engine */
                        temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL);
                        temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
 
        return 0;
 }
 
+static void soc15_sdma_doorbell_range_init(struct amdgpu_device *adev)
+{
+       int i;
+
+       /* sdma doorbell range is programed by hypervisor */
+       if (!amdgpu_sriov_vf(adev)) {
+               for (i = 0; i < adev->sdma.num_instances; i++) {
+                       adev->nbio.funcs->sdma_doorbell_range(adev, i,
+                               true, adev->doorbell_index.sdma_engine[i] << 1,
+                               adev->doorbell_index.sdma_doorbell_range);
+               }
+       }
+}
+
 static int soc15_common_hw_init(void *handle)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
        /* enable the doorbell aperture */
        soc15_enable_doorbell_aperture(adev, true);
+       /* HW doorbell routing policy: doorbell writing not
+        * in SDMA/IH/MM/ACV range will be routed to CP. So
+        * we need to init SDMA doorbell range prior
+        * to CP ip block init and ring test.  IH already
+        * happens before CP.
+        */
+       soc15_sdma_doorbell_range_init(adev);
 
        return 0;
 }