ARM: dts: qcom: ipq8064: fix and add some missing gsbi node

Add some tag for gsbi to make them usable for ipq8064 SoC. Add missing
gsbi7 i2c node and gsbi1 node.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Tested-by: Jonathan McDowell <noodles@earth.li>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220707010943.20857-8-ansuelsmth@gmail.com

diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 8d2f7c8bf6ac51c41178c7a20b82942784bb6028..69cf664851c63d4663f06491125b8a5795daf3df 100644 (file)
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -539,6 +539,44 @@
                        regulator;
                };
 
+               gsbi1: gsbi@12440000 {
+                       compatible = "qcom,gsbi-v1.0.0";
+                       reg = <0x12440000 0x100>;
+                       cell-index = <1>;
+                       clocks = <&gcc GSBI1_H_CLK>;
+                       clock-names = "iface";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges;
+
+                       syscon-tcsr = <&tcsr>;
+
+                       status = "disabled";
+
+                       gsbi1_serial: serial@12450000 {
+                               compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
+                               reg = <0x12450000 0x100>,
+                                     <0x12400000 0x03>;
+                               interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
+                               clock-names = "core", "iface";
+
+                               status = "disabled";
+                       };
+
+                       gsbi1_i2c: i2c@12460000 {
+                               compatible = "qcom,i2c-qup-v1.1.1";
+                               reg = <0x12460000 0x1000>;
+                               interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
+                               clock-names = "core", "iface";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               status = "disabled";
+                       };
+               };
+
                gsbi2: gsbi@12480000 {
                        compatible = "qcom,gsbi-v1.0.0";
                        cell-index = <2>;
@@ -562,7 +600,7 @@
                                status = "disabled";
                        };
 
-                       i2c@124a0000 {
+                       gsbi2_i2c: i2c@124a0000 {
                                compatible = "qcom,i2c-qup-v1.1.1";
                                reg = <0x124a0000 0x1000>;
                                interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
@@ -727,6 +765,20 @@
                                clock-names = "core", "iface";
                                status = "disabled";
                        };
+
+                       gsbi7_i2c: i2c@16680000 {
+                               compatible = "qcom,i2c-qup-v1.1.1";
+                               reg = <0x16680000 0x1000>;
+                               interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+
+                               clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
+                               clock-names = "core", "iface";
+
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               status = "disabled";
+                       };
                };
 
                rng@1a500000 {