drm/amd/powerplay: clear the swSMU code layer

With this cleanup, the APIs from amdgpu_smu.c will map to
ASIC specific ones directly. Those can be shared around
all SMU V11/V12 ASICs will be put in smu_v11_0.c and
smu_v12_0.c respectively.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index 700134d0ca71e7759634eb81741523d6a8b6c156..55a520a63712460f5d31b2883aea38e57fed0975 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -345,7 +345,7 @@ bool dm_pp_get_clock_levels_by_type(
                /* Error in pplib. Provide default values. */
                        return true;
                }
-       } else if (adev->smu.funcs && adev->smu.funcs->get_clock_by_type) {
+       } else if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->get_clock_by_type) {
                if (smu_get_clock_by_type(&adev->smu,
                                          dc_to_pp_clock_type(clk_type),
                                          &pp_clks)) {
@@ -365,7 +365,7 @@ bool dm_pp_get_clock_levels_by_type(
                        validation_clks.memory_max_clock = 80000;
                        validation_clks.level = 0;
                }
-       } else if (adev->smu.funcs && adev->smu.funcs->get_max_high_clocks) {
+       } else if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->get_max_high_clocks) {
                if (smu_get_max_high_clocks(&adev->smu, &validation_clks)) {
                        DRM_INFO("DM_PPLIB: Warning: using default validation clocks!\n");
                        validation_clks.engine_max_clock = 72000;
@@ -506,8 +506,8 @@ bool dm_pp_apply_clock_for_voltage_request(
                ret = adev->powerplay.pp_funcs->display_clock_voltage_request(
                        adev->powerplay.pp_handle,
                        &pp_clock_request);
-       else if (adev->smu.funcs &&
-                adev->smu.funcs->display_clock_voltage_request)
+       else if (adev->smu.ppt_funcs &&
+                adev->smu.ppt_funcs->display_clock_voltage_request)
                ret = smu_display_clock_voltage_request(&adev->smu,
                                                        &pp_clock_request);
        if (ret)
@@ -527,7 +527,7 @@ bool dm_pp_get_static_clocks(
                ret = adev->powerplay.pp_funcs->get_current_clocks(
                        adev->powerplay.pp_handle,
                        &pp_clk_info);
-       else if (adev->smu.funcs)
+       else if (adev->smu.ppt_funcs)
                ret = smu_get_current_clocks(&adev->smu, &pp_clk_info);
        if (ret)
                return false;
@@ -603,7 +603,7 @@ void pp_rv_set_pme_wa_enable(struct pp_smu *pp)
 
        if (pp_funcs && pp_funcs->notify_smu_enable_pwe)
                pp_funcs->notify_smu_enable_pwe(pp_handle);
-       else if (adev->smu.funcs)
+       else if (adev->smu.ppt_funcs)
                smu_notify_smu_enable_pwe(&adev->smu);
 }
 
@@ -717,10 +717,10 @@ enum pp_smu_status pp_nv_set_pme_wa_enable(struct pp_smu *pp)
        struct amdgpu_device *adev = ctx->driver_context;
        struct smu_context *smu = &adev->smu;
 
-       if (!smu->funcs)
+       if (!smu->ppt_funcs)
                return PP_SMU_RESULT_UNSUPPORTED;
 
-       /* 0: successful or smu.funcs->set_azalia_d3_pme = NULL;  1: fail */
+       /* 0: successful or smu.ppt_funcs->set_azalia_d3_pme = NULL;  1: fail */
        if (smu_set_azalia_d3_pme(smu))
                return PP_SMU_RESULT_FAIL;
 
@@ -733,10 +733,10 @@ enum pp_smu_status pp_nv_set_display_count(struct pp_smu *pp, int count)
        struct amdgpu_device *adev = ctx->driver_context;
        struct smu_context *smu = &adev->smu;
 
-       if (!smu->funcs)
+       if (!smu->ppt_funcs)
                return PP_SMU_RESULT_UNSUPPORTED;
 
-       /* 0: successful or smu.funcs->set_display_count = NULL;  1: fail */
+       /* 0: successful or smu.ppt_funcs->set_display_count = NULL;  1: fail */
        if (smu_set_display_count(smu, count))
                return PP_SMU_RESULT_FAIL;
 
@@ -749,10 +749,10 @@ enum pp_smu_status pp_nv_set_min_deep_sleep_dcfclk(struct pp_smu *pp, int mhz)
        struct amdgpu_device *adev = ctx->driver_context;
        struct smu_context *smu = &adev->smu;
 
-       if (!smu->funcs)
+       if (!smu->ppt_funcs)
                return PP_SMU_RESULT_UNSUPPORTED;
 
-       /* 0: successful or smu.funcs->set_deep_sleep_dcefclk = NULL;1: fail */
+       /* 0: successful or smu.ppt_funcs->set_deep_sleep_dcefclk = NULL;1: fail */
        if (smu_set_deep_sleep_dcefclk(smu, mhz))
                return PP_SMU_RESULT_FAIL;
 
@@ -767,13 +767,13 @@ enum pp_smu_status pp_nv_set_hard_min_dcefclk_by_freq(
        struct smu_context *smu = &adev->smu;
        struct pp_display_clock_request clock_req;
 
-       if (!smu->funcs)
+       if (!smu->ppt_funcs)
                return PP_SMU_RESULT_UNSUPPORTED;
 
        clock_req.clock_type = amd_pp_dcef_clock;
        clock_req.clock_freq_in_khz = mhz * 1000;
 
-       /* 0: successful or smu.funcs->display_clock_voltage_request = NULL
+       /* 0: successful or smu.ppt_funcs->display_clock_voltage_request = NULL
         * 1: fail
         */
        if (smu_display_clock_voltage_request(smu, &clock_req))
@@ -789,13 +789,13 @@ enum pp_smu_status pp_nv_set_hard_min_uclk_by_freq(struct pp_smu *pp, int mhz)
        struct smu_context *smu = &adev->smu;
        struct pp_display_clock_request clock_req;
 
-       if (!smu->funcs)
+       if (!smu->ppt_funcs)
                return PP_SMU_RESULT_UNSUPPORTED;
 
        clock_req.clock_type = amd_pp_mem_clock;
        clock_req.clock_freq_in_khz = mhz * 1000;
 
-       /* 0: successful or smu.funcs->display_clock_voltage_request = NULL
+       /* 0: successful or smu.ppt_funcs->display_clock_voltage_request = NULL
         * 1: fail
         */
        if (smu_display_clock_voltage_request(smu, &clock_req))
@@ -825,7 +825,7 @@ enum pp_smu_status pp_nv_set_voltage_by_freq(struct pp_smu *pp,
        struct smu_context *smu = &adev->smu;
        struct pp_display_clock_request clock_req;
 
-       if (!smu->funcs)
+       if (!smu->ppt_funcs)
                return PP_SMU_RESULT_UNSUPPORTED;
 
        switch (clock_id) {
@@ -843,7 +843,7 @@ enum pp_smu_status pp_nv_set_voltage_by_freq(struct pp_smu *pp,
        }
        clock_req.clock_freq_in_khz = mhz * 1000;
 
-       /* 0: successful or smu.funcs->display_clock_voltage_request = NULL
+       /* 0: successful or smu.ppt_funcs->display_clock_voltage_request = NULL
         * 1: fail
         */
        if (smu_display_clock_voltage_request(smu, &clock_req))
@@ -859,10 +859,10 @@ enum pp_smu_status pp_nv_get_maximum_sustainable_clocks(
        struct amdgpu_device *adev = ctx->driver_context;
        struct smu_context *smu = &adev->smu;
 
-       if (!smu->funcs)
+       if (!smu->ppt_funcs)
                return PP_SMU_RESULT_UNSUPPORTED;
 
-       if (!smu->funcs->get_max_sustainable_clocks_by_dc)
+       if (!smu->ppt_funcs->get_max_sustainable_clocks_by_dc)
                return PP_SMU_RESULT_UNSUPPORTED;
 
        if (!smu_get_max_sustainable_clocks_by_dc(smu, max_clocks))
@@ -924,7 +924,7 @@ enum pp_smu_status pp_rn_set_wm_ranges(struct pp_smu *pp,
                        wm_with_clock_ranges.wm_mcif_clocks_ranges;
        int32_t i;
 
-       if (!smu->funcs)
+       if (!smu->ppt_funcs)
                return PP_SMU_RESULT_UNSUPPORTED;
 
        wm_with_clock_ranges.num_wm_dmif_sets = ranges->num_reader_wm_sets;

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 62ef8c43e14e7b84ea4baf6db6eb0f8aabb3e0e3..26923aa5aea1019a477116c6e4940778af3588a1 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -31,6 +31,10 @@
 #include "smu_v12_0.h"
 #include "atom.h"
 #include "amd_pcie.h"
+#include "vega20_ppt.h"
+#include "arcturus_ppt.h"
+#include "navi10_ppt.h"
+#include "renoir_ppt.h"
 
 #undef __SMU_DUMMY_MAP
 #define __SMU_DUMMY_MAP(type)  #type
@@ -703,23 +707,26 @@ static int smu_set_funcs(struct amdgpu_device *adev)
 
        switch (adev->asic_type) {
        case CHIP_VEGA20:
+               vega20_set_ppt_funcs(smu);
+               break;
        case CHIP_NAVI10:
        case CHIP_NAVI14:
        case CHIP_NAVI12:
+               navi10_set_ppt_funcs(smu);
+               break;
        case CHIP_ARCTURUS:
-               if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
-                       smu->od_enabled = true;
-               smu_v11_0_set_smu_funcs(smu);
+               arcturus_set_ppt_funcs(smu);
                break;
        case CHIP_RENOIR:
-               if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
-                       smu->od_enabled = true;
-               smu_v12_0_set_smu_funcs(smu);
+               renoir_set_ppt_funcs(smu);
                break;
        default:
                return -EINVAL;
        }
 
+       if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
+               smu->od_enabled = true;
+
        return 0;
 }
 
@@ -1177,16 +1184,16 @@ static int smu_start_smc_engine(struct smu_context *smu)
 
        if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
                if (adev->asic_type < CHIP_NAVI10) {
-                       if (smu->funcs->load_microcode) {
-                               ret = smu->funcs->load_microcode(smu);
+                       if (smu->ppt_funcs->load_microcode) {
+                               ret = smu->ppt_funcs->load_microcode(smu);
                                if (ret)
                                        return ret;
                        }
                }
        }
 
-       if (smu->funcs->check_fw_status) {
-               ret = smu->funcs->check_fw_status(smu);
+       if (smu->ppt_funcs->check_fw_status) {
+               ret = smu->ppt_funcs->check_fw_status(smu);
                if (ret)
                        pr_err("SMC is not ready\n");
        }
@@ -1397,8 +1404,8 @@ int smu_display_configuration_change(struct smu_context *smu,
 
        mutex_lock(&smu->mutex);
 
-       if (smu->funcs->set_deep_sleep_dcefclk)
-               smu->funcs->set_deep_sleep_dcefclk(smu,
+       if (smu->ppt_funcs->set_deep_sleep_dcefclk)
+               smu->ppt_funcs->set_deep_sleep_dcefclk(smu,
                                display_config->min_dcef_deep_sleep_set_clk / 100);
 
        for (index = 0; index < display_config->num_path_including_non_display; index++) {
@@ -1952,8 +1959,8 @@ int smu_load_microcode(struct smu_context *smu)
 
        mutex_lock(&smu->mutex);
 
-       if (smu->funcs->load_microcode)
-               ret = smu->funcs->load_microcode(smu);
+       if (smu->ppt_funcs->load_microcode)
+               ret = smu->ppt_funcs->load_microcode(smu);
 
        mutex_unlock(&smu->mutex);
 
@@ -1966,8 +1973,8 @@ int smu_check_fw_status(struct smu_context *smu)
 
        mutex_lock(&smu->mutex);
 
-       if (smu->funcs->check_fw_status)
-               ret = smu->funcs->check_fw_status(smu);
+       if (smu->ppt_funcs->check_fw_status)
+               ret = smu->ppt_funcs->check_fw_status(smu);
 
        mutex_unlock(&smu->mutex);
 
@@ -1980,8 +1987,8 @@ int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
 
        mutex_lock(&smu->mutex);
 
-       if (smu->funcs->set_gfx_cgpg)
-               ret = smu->funcs->set_gfx_cgpg(smu, enabled);
+       if (smu->ppt_funcs->set_gfx_cgpg)
+               ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled);
 
        mutex_unlock(&smu->mutex);
 
@@ -1994,8 +2001,8 @@ int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed)
 
        mutex_lock(&smu->mutex);
 
-       if (smu->funcs->set_fan_speed_rpm)
-               ret = smu->funcs->set_fan_speed_rpm(smu, speed);
+       if (smu->ppt_funcs->set_fan_speed_rpm)
+               ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);
 
        mutex_unlock(&smu->mutex);
 
@@ -2027,8 +2034,8 @@ int smu_set_power_limit(struct smu_context *smu, uint32_t limit)
 
        mutex_lock(&smu->mutex);
 
-       if (smu->funcs->set_power_limit)
-               ret = smu->funcs->set_power_limit(smu, limit);
+       if (smu->ppt_funcs->set_power_limit)
+               ret = smu->ppt_funcs->set_power_limit(smu, limit);
 
        mutex_unlock(&smu->mutex);
 
@@ -2149,8 +2156,8 @@ int smu_get_fan_control_mode(struct smu_context *smu)
 
        mutex_lock(&smu->mutex);
 
-       if (smu->funcs->get_fan_control_mode)
-               ret = smu->funcs->get_fan_control_mode(smu);
+       if (smu->ppt_funcs->get_fan_control_mode)
+               ret = smu->ppt_funcs->get_fan_control_mode(smu);
 
        mutex_unlock(&smu->mutex);
 
@@ -2163,8 +2170,8 @@ int smu_set_fan_control_mode(struct smu_context *smu, int value)
 
        mutex_lock(&smu->mutex);
 
-       if (smu->funcs->set_fan_control_mode)
-               ret = smu->funcs->set_fan_control_mode(smu, value);
+       if (smu->ppt_funcs->set_fan_control_mode)
+               ret = smu->ppt_funcs->set_fan_control_mode(smu, value);
 
        mutex_unlock(&smu->mutex);
 
@@ -2191,8 +2198,8 @@ int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
 
        mutex_lock(&smu->mutex);
 
-       if (smu->funcs->set_fan_speed_percent)
-               ret = smu->funcs->set_fan_speed_percent(smu, speed);
+       if (smu->ppt_funcs->set_fan_speed_percent)
+               ret = smu->ppt_funcs->set_fan_speed_percent(smu, speed);
 
        mutex_unlock(&smu->mutex);
 
@@ -2219,8 +2226,8 @@ int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk)
 
        mutex_lock(&smu->mutex);
 
-       if (smu->funcs->set_deep_sleep_dcefclk)
-               ret = smu->funcs->set_deep_sleep_dcefclk(smu, clk);
+       if (smu->ppt_funcs->set_deep_sleep_dcefclk)
+               ret = smu->ppt_funcs->set_deep_sleep_dcefclk(smu, clk);
 
        mutex_unlock(&smu->mutex);
 
@@ -2233,8 +2240,8 @@ int smu_set_active_display_count(struct smu_context *smu, uint32_t count)
 
        mutex_lock(&smu->mutex);
 
-       if (smu->funcs->set_active_display_count)
-               ret = smu->funcs->set_active_display_count(smu, count);
+       if (smu->ppt_funcs->set_active_display_count)
+               ret = smu->ppt_funcs->set_active_display_count(smu, count);
 
        mutex_unlock(&smu->mutex);
 
@@ -2249,8 +2256,8 @@ int smu_get_clock_by_type(struct smu_context *smu,
 
        mutex_lock(&smu->mutex);
 
-       if (smu->funcs->get_clock_by_type)
-               ret = smu->funcs->get_clock_by_type(smu, type, clocks);
+       if (smu->ppt_funcs->get_clock_by_type)
+               ret = smu->ppt_funcs->get_clock_by_type(smu, type, clocks);
 
        mutex_unlock(&smu->mutex);
 
@@ -2264,8 +2271,8 @@ int smu_get_max_high_clocks(struct smu_context *smu,
 
        mutex_lock(&smu->mutex);
 
-       if (smu->funcs->get_max_high_clocks)
-               ret = smu->funcs->get_max_high_clocks(smu, clocks);
+       if (smu->ppt_funcs->get_max_high_clocks)
+               ret = smu->ppt_funcs->get_max_high_clocks(smu, clocks);
 
        mutex_unlock(&smu->mutex);
 
@@ -2312,8 +2319,8 @@ int smu_display_clock_voltage_request(struct smu_context *smu,
 
        mutex_lock(&smu->mutex);
 
-       if (smu->funcs->display_clock_voltage_request)
-               ret = smu->funcs->display_clock_voltage_request(smu, clock_req);
+       if (smu->ppt_funcs->display_clock_voltage_request)
+               ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req);
 
        mutex_unlock(&smu->mutex);
 
@@ -2341,8 +2348,8 @@ int smu_notify_smu_enable_pwe(struct smu_context *smu)
 
        mutex_lock(&smu->mutex);
 
-       if (smu->funcs->notify_smu_enable_pwe)
-               ret = smu->funcs->notify_smu_enable_pwe(smu);
+       if (smu->ppt_funcs->notify_smu_enable_pwe)
+               ret = smu->ppt_funcs->notify_smu_enable_pwe(smu);
 
        mutex_unlock(&smu->mutex);
 
@@ -2356,8 +2363,8 @@ int smu_set_xgmi_pstate(struct smu_context *smu,
 
        mutex_lock(&smu->mutex);
 
-       if (smu->funcs->set_xgmi_pstate)
-               ret = smu->funcs->set_xgmi_pstate(smu, pstate);
+       if (smu->ppt_funcs->set_xgmi_pstate)
+               ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate);
 
        mutex_unlock(&smu->mutex);
 
@@ -2370,8 +2377,8 @@ int smu_set_azalia_d3_pme(struct smu_context *smu)
 
        mutex_lock(&smu->mutex);
 
-       if (smu->funcs->set_azalia_d3_pme)
-               ret = smu->funcs->set_azalia_d3_pme(smu);
+       if (smu->ppt_funcs->set_azalia_d3_pme)
+               ret = smu->ppt_funcs->set_azalia_d3_pme(smu);
 
        mutex_unlock(&smu->mutex);
 
@@ -2384,8 +2391,8 @@ bool smu_baco_is_support(struct smu_context *smu)
 
        mutex_lock(&smu->mutex);
 
-       if (smu->funcs->baco_is_support)
-               ret = smu->funcs->baco_is_support(smu);
+       if (smu->ppt_funcs->baco_is_support)
+               ret = smu->ppt_funcs->baco_is_support(smu);
 
        mutex_unlock(&smu->mutex);
 
@@ -2394,11 +2401,11 @@ bool smu_baco_is_support(struct smu_context *smu)
 
 int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state)
 {
-       if (smu->funcs->baco_get_state)
+       if (smu->ppt_funcs->baco_get_state)
                return -EINVAL;
 
        mutex_lock(&smu->mutex);
-       *state = smu->funcs->baco_get_state(smu);
+       *state = smu->ppt_funcs->baco_get_state(smu);
        mutex_unlock(&smu->mutex);
 
        return 0;
@@ -2410,8 +2417,8 @@ int smu_baco_reset(struct smu_context *smu)
 
        mutex_lock(&smu->mutex);
 
-       if (smu->funcs->baco_reset)
-               ret = smu->funcs->baco_reset(smu);
+       if (smu->ppt_funcs->baco_reset)
+               ret = smu->ppt_funcs->baco_reset(smu);
 
        mutex_unlock(&smu->mutex);
 
@@ -2424,8 +2431,8 @@ int smu_mode2_reset(struct smu_context *smu)
 
        mutex_lock(&smu->mutex);
 
-       if (smu->funcs->mode2_reset)
-               ret = smu->funcs->mode2_reset(smu);
+       if (smu->ppt_funcs->mode2_reset)
+               ret = smu->ppt_funcs->mode2_reset(smu);
 
        mutex_unlock(&smu->mutex);
 
@@ -2439,8 +2446,8 @@ int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
 
        mutex_lock(&smu->mutex);
 
-       if (smu->funcs->get_max_sustainable_clocks_by_dc)
-               ret = smu->funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
+       if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc)
+               ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
 
        mutex_unlock(&smu->mutex);
 

diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index fb02d6c844151396a69caccf2ceb57d10dd58bd4..021fabccbd26dd2a1978263eda29f1960325223e 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -1048,7 +1048,7 @@ static int arcturus_read_sensor(struct smu_context *smu,
                *size = 4;
                break;
        default:
-               ret = smu_smc_read_sensor(smu, sensor, data, size);
+               ret = smu_v11_0_read_sensor(smu, sensor, data, size);
        }
        mutex_unlock(&smu->sensor_lock);
 
@@ -1964,6 +1964,55 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
        .get_power_limit = arcturus_get_power_limit,
        .is_dpm_running = arcturus_is_dpm_running,
        .dpm_set_uvd_enable = arcturus_dpm_set_uvd_enable,
+       .init_microcode = smu_v11_0_init_microcode,
+       .load_microcode = smu_v11_0_load_microcode,
+       .init_smc_tables = smu_v11_0_init_smc_tables,
+       .fini_smc_tables = smu_v11_0_fini_smc_tables,
+       .init_power = smu_v11_0_init_power,
+       .fini_power = smu_v11_0_fini_power,
+       .check_fw_status = smu_v11_0_check_fw_status,
+       .setup_pptable = smu_v11_0_setup_pptable,
+       .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
+       .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
+       .check_pptable = smu_v11_0_check_pptable,
+       .parse_pptable = smu_v11_0_parse_pptable,
+       .populate_smc_tables = smu_v11_0_populate_smc_pptable,
+       .check_fw_version = smu_v11_0_check_fw_version,
+       .write_pptable = smu_v11_0_write_pptable,
+       .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
+       .set_tool_table_location = smu_v11_0_set_tool_table_location,
+       .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
+       .system_features_control = smu_v11_0_system_features_control,
+       .send_smc_msg = smu_v11_0_send_msg,
+       .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
+       .read_smc_arg = smu_v11_0_read_arg,
+       .init_display_count = smu_v11_0_init_display_count,
+       .set_allowed_mask = smu_v11_0_set_allowed_mask,
+       .get_enabled_mask = smu_v11_0_get_enabled_mask,
+       .notify_display_change = smu_v11_0_notify_display_change,
+       .set_power_limit = smu_v11_0_set_power_limit,
+       .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
+       .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
+       .start_thermal_control = smu_v11_0_start_thermal_control,
+       .stop_thermal_control = smu_v11_0_stop_thermal_control,
+       .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
+       .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
+       .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
+       .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
+       .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
+       .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
+       .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
+       .gfx_off_control = smu_v11_0_gfx_off_control,
+       .register_irq_handler = smu_v11_0_register_irq_handler,
+       .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
+       .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
+       .baco_is_support= smu_v11_0_baco_is_support,
+       .baco_get_state = smu_v11_0_baco_get_state,
+       .baco_set_state = smu_v11_0_baco_set_state,
+       .baco_reset = smu_v11_0_baco_reset,
+       .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
+       .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
+       .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
 };
 
 void arcturus_set_ppt_funcs(struct smu_context *smu)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 79fe32acc83836db52bc760495a14494acdbef45..402a021f237b06e1d6b0e072cabb2c9fdbeb1316 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -347,7 +347,6 @@ struct smu_context
        struct amdgpu_device            *adev;
        struct amdgpu_irq_src           *irq_source;
 
-       const struct smu_funcs          *funcs;
        const struct pptable_funcs      *ppt_funcs;
        struct mutex                    mutex;
        struct mutex                    sensor_lock;
@@ -471,16 +470,12 @@ struct pptable_funcs {
        int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state);
        int (*update_pcie_parameters)(struct smu_context *smu, uint32_t pcie_gen_cap, uint32_t pcie_width_cap);
        int (*get_dpm_clock_table)(struct smu_context *smu, struct dpm_clocks *clock_table);
-};
-
-struct smu_funcs
-{
        int (*init_microcode)(struct smu_context *smu);
+       int (*load_microcode)(struct smu_context *smu);
        int (*init_smc_tables)(struct smu_context *smu);
        int (*fini_smc_tables)(struct smu_context *smu);
        int (*init_power)(struct smu_context *smu);
        int (*fini_power)(struct smu_context *smu);
-       int (*load_microcode)(struct smu_context *smu);
        int (*check_fw_status)(struct smu_context *smu);
        int (*setup_pptable)(struct smu_context *smu);
        int (*get_vbios_bootup_values)(struct smu_context *smu);
@@ -510,8 +505,6 @@ struct smu_funcs
        int (*init_max_sustainable_clocks)(struct smu_context *smu);
        int (*start_thermal_control)(struct smu_context *smu);
        int (*stop_thermal_control)(struct smu_context *smu);
-       int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor,
-                          void *data, uint32_t *size);
        int (*set_deep_sleep_dcefclk)(struct smu_context *smu, uint32_t clk);
        int (*set_active_display_count)(struct smu_context *smu, uint32_t count);
        int (*store_cc6_data)(struct smu_context *smu, uint32_t separation_time,

diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index 519f0b82970b64e338deed5697d27391afe31764..abd4debb3def149f45b59c10f5d8d0a2b209114b 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -130,6 +130,124 @@ enum smu_v11_0_baco_seq {
        BACO_SEQ_COUNT,
 };
 
-void smu_v11_0_set_smu_funcs(struct smu_context *smu);
+int smu_v11_0_init_microcode(struct smu_context *smu);
+
+int smu_v11_0_load_microcode(struct smu_context *smu);
+
+int smu_v11_0_init_smc_tables(struct smu_context *smu);
+
+int smu_v11_0_fini_smc_tables(struct smu_context *smu);
+
+int smu_v11_0_init_power(struct smu_context *smu);
+
+int smu_v11_0_fini_power(struct smu_context *smu);
+
+int smu_v11_0_check_fw_status(struct smu_context *smu);
+
+int smu_v11_0_setup_pptable(struct smu_context *smu);
+
+int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu);
+
+int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu);
+
+int smu_v11_0_check_pptable(struct smu_context *smu);
+
+int smu_v11_0_parse_pptable(struct smu_context *smu);
+
+int smu_v11_0_populate_smc_pptable(struct smu_context *smu);
+
+int smu_v11_0_check_fw_version(struct smu_context *smu);
+
+int smu_v11_0_write_pptable(struct smu_context *smu);
+
+int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu);
+
+int smu_v11_0_set_tool_table_location(struct smu_context *smu);
+
+int smu_v11_0_notify_memory_pool_location(struct smu_context *smu);
+
+int smu_v11_0_system_features_control(struct smu_context *smu,
+                                            bool en);
+
+int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg);
+
+int
+smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
+                             uint32_t param);
+
+int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg);
+
+int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count);
+
+int smu_v11_0_set_allowed_mask(struct smu_context *smu);
+
+int smu_v11_0_get_enabled_mask(struct smu_context *smu,
+                                     uint32_t *feature_mask, uint32_t num);
+
+int smu_v11_0_notify_display_change(struct smu_context *smu);
+
+int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n);
+
+int smu_v11_0_get_current_clk_freq(struct smu_context *smu,
+                                         enum smu_clk_type clk_id,
+                                         uint32_t *value);
+
+int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu);
+
+int smu_v11_0_start_thermal_control(struct smu_context *smu);
+
+int smu_v11_0_stop_thermal_control(struct smu_context *smu);
+
+int smu_v11_0_read_sensor(struct smu_context *smu,
+                                enum amd_pp_sensors sensor,
+                                void *data, uint32_t *size);
+
+int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk);
+
+int
+smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
+                                       struct pp_display_clock_request
+                                       *clock_req);
+
+uint32_t
+smu_v11_0_get_fan_control_mode(struct smu_context *smu);
+
+int
+smu_v11_0_set_fan_control_mode(struct smu_context *smu,
+                              uint32_t mode);
+
+int
+smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed);
+
+int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
+                                      uint32_t speed);
+
+int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
+                                    uint32_t pstate);
+
+int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable);
+
+int smu_v11_0_register_irq_handler(struct smu_context *smu);
+
+int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu);
+
+int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
+               struct pp_smu_nv_clock_table *max_clocks);
+
+bool smu_v11_0_baco_is_support(struct smu_context *smu);
+
+enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu);
+
+int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state);
+
+int smu_v11_0_baco_reset(struct smu_context *smu);
+
+int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
+                                                uint32_t *min, uint32_t *max);
+
+int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
+                           uint32_t min, uint32_t max);
+
+int smu_v11_0_override_pcie_parameters(struct smu_context *smu);
 
 #endif

diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
index acf3db12f59f84abf66ba47a8a9e5fdcf6d3a049..9b9f5df0911c5e87326db561860151521bea3af6 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
@@ -37,6 +37,45 @@ struct smu_12_0_cmn2aisc_mapping {
        int     map_to;
 };
 
-void smu_v12_0_set_smu_funcs(struct smu_context *smu);
+int smu_v12_0_send_msg_without_waiting(struct smu_context *smu,
+                                             uint16_t msg);
+
+int smu_v12_0_read_arg(struct smu_context *smu, uint32_t *arg);
+
+int smu_v12_0_wait_for_response(struct smu_context *smu);
+
+int smu_v12_0_send_msg(struct smu_context *smu, uint16_t msg);
+
+int
+smu_v12_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
+                             uint32_t param);
+
+int smu_v12_0_check_fw_status(struct smu_context *smu);
+
+int smu_v12_0_check_fw_version(struct smu_context *smu);
+
+int smu_v12_0_powergate_sdma(struct smu_context *smu, bool gate);
+
+int smu_v12_0_powergate_vcn(struct smu_context *smu, bool gate);
+
+int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable);
+
+uint32_t smu_v12_0_get_gfxoff_status(struct smu_context *smu);
+
+int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable);
+
+int smu_v12_0_init_smc_tables(struct smu_context *smu);
+
+int smu_v12_0_fini_smc_tables(struct smu_context *smu);
+
+int smu_v12_0_populate_smc_tables(struct smu_context *smu);
+
+int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
+                                                uint32_t *min, uint32_t *max);
+
+int smu_v12_0_mode2_reset(struct smu_context *smu);
+
+int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
+                           uint32_t min, uint32_t max);
 
 #endif

diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index b99e6c80a9e1fa8a22f657b45544eb036646aa3f..769f9451d90437d5ba1017f2990f28c1805e8fc0 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1269,8 +1269,7 @@ static int navi10_notify_smc_dispaly_config(struct smu_context *smu)
                clock_req.clock_type = amd_pp_dcef_clock;
                clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
 
-               if (smu->funcs->display_clock_voltage_request)
-                       ret = smu->funcs->display_clock_voltage_request(smu, &clock_req);
+               ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
                if (!ret) {
                        if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
                                ret = smu_send_smc_msg_with_param(smu,
@@ -1425,7 +1424,7 @@ static int navi10_read_sensor(struct smu_context *smu,
                *size = 4;
                break;
        default:
-               ret = smu_smc_read_sensor(smu, sensor, data, size);
+               ret = smu_v11_0_read_sensor(smu, sensor, data, size);
        }
        mutex_unlock(&smu->sensor_lock);
 
@@ -1694,6 +1693,55 @@ static const struct pptable_funcs navi10_ppt_funcs = {
        .display_disable_memory_clock_switch = navi10_display_disable_memory_clock_switch,
        .get_power_limit = navi10_get_power_limit,
        .update_pcie_parameters = navi10_update_pcie_parameters,
+       .init_microcode = smu_v11_0_init_microcode,
+       .load_microcode = smu_v11_0_load_microcode,
+       .init_smc_tables = smu_v11_0_init_smc_tables,
+       .fini_smc_tables = smu_v11_0_fini_smc_tables,
+       .init_power = smu_v11_0_init_power,
+       .fini_power = smu_v11_0_fini_power,
+       .check_fw_status = smu_v11_0_check_fw_status,
+       .setup_pptable = smu_v11_0_setup_pptable,
+       .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
+       .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
+       .check_pptable = smu_v11_0_check_pptable,
+       .parse_pptable = smu_v11_0_parse_pptable,
+       .populate_smc_tables = smu_v11_0_populate_smc_pptable,
+       .check_fw_version = smu_v11_0_check_fw_version,
+       .write_pptable = smu_v11_0_write_pptable,
+       .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
+       .set_tool_table_location = smu_v11_0_set_tool_table_location,
+       .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
+       .system_features_control = smu_v11_0_system_features_control,
+       .send_smc_msg = smu_v11_0_send_msg,
+       .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
+       .read_smc_arg = smu_v11_0_read_arg,
+       .init_display_count = smu_v11_0_init_display_count,
+       .set_allowed_mask = smu_v11_0_set_allowed_mask,
+       .get_enabled_mask = smu_v11_0_get_enabled_mask,
+       .notify_display_change = smu_v11_0_notify_display_change,
+       .set_power_limit = smu_v11_0_set_power_limit,
+       .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
+       .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
+       .start_thermal_control = smu_v11_0_start_thermal_control,
+       .stop_thermal_control = smu_v11_0_stop_thermal_control,
+       .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
+       .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
+       .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
+       .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
+       .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
+       .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
+       .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
+       .gfx_off_control = smu_v11_0_gfx_off_control,
+       .register_irq_handler = smu_v11_0_register_irq_handler,
+       .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
+       .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
+       .baco_is_support= smu_v11_0_baco_is_support,
+       .baco_get_state = smu_v11_0_baco_get_state,
+       .baco_set_state = smu_v11_0_baco_set_state,
+       .baco_reset = smu_v11_0_baco_reset,
+       .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
+       .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
+       .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
 };
 
 void navi10_set_ppt_funcs(struct smu_context *smu)

diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 6df91b1a9daa1b1d9793e93475acb05bc982a97f..45c5f54e60d842feda878224a9178fc1493a511d 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -691,6 +691,21 @@ static const struct pptable_funcs renoir_ppt_funcs = {
        .get_dpm_clock_table = renoir_get_dpm_clock_table,
        .set_watermarks_table = renoir_set_watermarks_table,
        .get_power_profile_mode = renoir_get_power_profile_mode,
+       .check_fw_status = smu_v12_0_check_fw_status,
+       .check_fw_version = smu_v12_0_check_fw_version,
+       .powergate_sdma = smu_v12_0_powergate_sdma,
+       .powergate_vcn = smu_v12_0_powergate_vcn,
+       .send_smc_msg = smu_v12_0_send_msg,
+       .send_smc_msg_with_param = smu_v12_0_send_msg_with_param,
+       .read_smc_arg = smu_v12_0_read_arg,
+       .set_gfx_cgpg = smu_v12_0_set_gfx_cgpg,
+       .gfx_off_control = smu_v12_0_gfx_off_control,
+       .init_smc_tables = smu_v12_0_init_smc_tables,
+       .fini_smc_tables = smu_v12_0_fini_smc_tables,
+       .populate_smc_tables = smu_v12_0_populate_smc_tables,
+       .get_dpm_ultimate_freq = smu_v12_0_get_dpm_ultimate_freq,
+       .mode2_reset = smu_v12_0_mode2_reset,
+       .set_soft_freq_limited_range = smu_v12_0_set_soft_freq_limited_range,
 };
 
 void renoir_set_ppt_funcs(struct smu_context *smu)

diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h b/drivers/gpu/drm/amd/powerplay/smu_internal.h
index c26eede7e36af749425acb9229694485c9eb46eb..8bcda78713099341df00bc67f11620e4ae3381e7 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/smu_internal.h
+++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h
@@ -26,73 +26,73 @@
 #include "amdgpu_smu.h"
 
 #define smu_init_microcode(smu) \
-       ((smu)->funcs->init_microcode ? (smu)->funcs->init_microcode((smu)) : 0)
+       ((smu)->ppt_funcs->init_microcode ? (smu)->ppt_funcs->init_microcode((smu)) : 0)
 #define smu_init_smc_tables(smu) \
-       ((smu)->funcs->init_smc_tables ? (smu)->funcs->init_smc_tables((smu)) : 0)
+       ((smu)->ppt_funcs->init_smc_tables ? (smu)->ppt_funcs->init_smc_tables((smu)) : 0)
 #define smu_fini_smc_tables(smu) \
-       ((smu)->funcs->fini_smc_tables ? (smu)->funcs->fini_smc_tables((smu)) : 0)
+       ((smu)->ppt_funcs->fini_smc_tables ? (smu)->ppt_funcs->fini_smc_tables((smu)) : 0)
 #define smu_init_power(smu) \
-       ((smu)->funcs->init_power ? (smu)->funcs->init_power((smu)) : 0)
+       ((smu)->ppt_funcs->init_power ? (smu)->ppt_funcs->init_power((smu)) : 0)
 #define smu_fini_power(smu) \
-       ((smu)->funcs->fini_power ? (smu)->funcs->fini_power((smu)) : 0)
+       ((smu)->ppt_funcs->fini_power ? (smu)->ppt_funcs->fini_power((smu)) : 0)
 
 #define smu_setup_pptable(smu) \
-       ((smu)->funcs->setup_pptable ? (smu)->funcs->setup_pptable((smu)) : 0)
+       ((smu)->ppt_funcs->setup_pptable ? (smu)->ppt_funcs->setup_pptable((smu)) : 0)
 #define smu_powergate_sdma(smu, gate) \
-       ((smu)->funcs->powergate_sdma ? (smu)->funcs->powergate_sdma((smu), (gate)) : 0)
+       ((smu)->ppt_funcs->powergate_sdma ? (smu)->ppt_funcs->powergate_sdma((smu), (gate)) : 0)
 #define smu_powergate_vcn(smu, gate) \
-       ((smu)->funcs->powergate_vcn ? (smu)->funcs->powergate_vcn((smu), (gate)) : 0)
+       ((smu)->ppt_funcs->powergate_vcn ? (smu)->ppt_funcs->powergate_vcn((smu), (gate)) : 0)
 
 #define smu_get_vbios_bootup_values(smu) \
-       ((smu)->funcs->get_vbios_bootup_values ? (smu)->funcs->get_vbios_bootup_values((smu)) : 0)
+       ((smu)->ppt_funcs->get_vbios_bootup_values ? (smu)->ppt_funcs->get_vbios_bootup_values((smu)) : 0)
 #define smu_get_clk_info_from_vbios(smu) \
-       ((smu)->funcs->get_clk_info_from_vbios ? (smu)->funcs->get_clk_info_from_vbios((smu)) : 0)
+       ((smu)->ppt_funcs->get_clk_info_from_vbios ? (smu)->ppt_funcs->get_clk_info_from_vbios((smu)) : 0)
 #define smu_check_pptable(smu) \
-       ((smu)->funcs->check_pptable ? (smu)->funcs->check_pptable((smu)) : 0)
+       ((smu)->ppt_funcs->check_pptable ? (smu)->ppt_funcs->check_pptable((smu)) : 0)
 #define smu_parse_pptable(smu) \
-       ((smu)->funcs->parse_pptable ? (smu)->funcs->parse_pptable((smu)) : 0)
+       ((smu)->ppt_funcs->parse_pptable ? (smu)->ppt_funcs->parse_pptable((smu)) : 0)
 #define smu_populate_smc_tables(smu) \
-       ((smu)->funcs->populate_smc_tables ? (smu)->funcs->populate_smc_tables((smu)) : 0)
+       ((smu)->ppt_funcs->populate_smc_tables ? (smu)->ppt_funcs->populate_smc_tables((smu)) : 0)
 #define smu_check_fw_version(smu) \
-       ((smu)->funcs->check_fw_version ? (smu)->funcs->check_fw_version((smu)) : 0)
+       ((smu)->ppt_funcs->check_fw_version ? (smu)->ppt_funcs->check_fw_version((smu)) : 0)
 #define smu_write_pptable(smu) \
-       ((smu)->funcs->write_pptable ? (smu)->funcs->write_pptable((smu)) : 0)
+       ((smu)->ppt_funcs->write_pptable ? (smu)->ppt_funcs->write_pptable((smu)) : 0)
 #define smu_set_min_dcef_deep_sleep(smu) \
-       ((smu)->funcs->set_min_dcef_deep_sleep ? (smu)->funcs->set_min_dcef_deep_sleep((smu)) : 0)
+       ((smu)->ppt_funcs->set_min_dcef_deep_sleep ? (smu)->ppt_funcs->set_min_dcef_deep_sleep((smu)) : 0)
 #define smu_set_tool_table_location(smu) \
-       ((smu)->funcs->set_tool_table_location ? (smu)->funcs->set_tool_table_location((smu)) : 0)
+       ((smu)->ppt_funcs->set_tool_table_location ? (smu)->ppt_funcs->set_tool_table_location((smu)) : 0)
 #define smu_notify_memory_pool_location(smu) \
-       ((smu)->funcs->notify_memory_pool_location ? (smu)->funcs->notify_memory_pool_location((smu)) : 0)
+       ((smu)->ppt_funcs->notify_memory_pool_location ? (smu)->ppt_funcs->notify_memory_pool_location((smu)) : 0)
 #define smu_gfx_off_control(smu, enable) \
-       ((smu)->funcs->gfx_off_control ? (smu)->funcs->gfx_off_control((smu), (enable)) : 0)
+       ((smu)->ppt_funcs->gfx_off_control ? (smu)->ppt_funcs->gfx_off_control((smu), (enable)) : 0)
 
 #define smu_set_last_dcef_min_deep_sleep_clk(smu) \
-       ((smu)->funcs->set_last_dcef_min_deep_sleep_clk ? (smu)->funcs->set_last_dcef_min_deep_sleep_clk((smu)) : 0)
+       ((smu)->ppt_funcs->set_last_dcef_min_deep_sleep_clk ? (smu)->ppt_funcs->set_last_dcef_min_deep_sleep_clk((smu)) : 0)
 #define smu_system_features_control(smu, en) \
-       ((smu)->funcs->system_features_control ? (smu)->funcs->system_features_control((smu), (en)) : 0)
+       ((smu)->ppt_funcs->system_features_control ? (smu)->ppt_funcs->system_features_control((smu), (en)) : 0)
 #define smu_init_max_sustainable_clocks(smu) \
-       ((smu)->funcs->init_max_sustainable_clocks ? (smu)->funcs->init_max_sustainable_clocks((smu)) : 0)
+       ((smu)->ppt_funcs->init_max_sustainable_clocks ? (smu)->ppt_funcs->init_max_sustainable_clocks((smu)) : 0)
 #define smu_set_default_od_settings(smu, initialize) \
        ((smu)->ppt_funcs->set_default_od_settings ? (smu)->ppt_funcs->set_default_od_settings((smu), (initialize)) : 0)
 
 #define smu_send_smc_msg(smu, msg) \
-       ((smu)->funcs->send_smc_msg? (smu)->funcs->send_smc_msg((smu), (msg)) : 0)
+       ((smu)->ppt_funcs->send_smc_msg? (smu)->ppt_funcs->send_smc_msg((smu), (msg)) : 0)
 #define smu_send_smc_msg_with_param(smu, msg, param) \
-       ((smu)->funcs->send_smc_msg_with_param? (smu)->funcs->send_smc_msg_with_param((smu), (msg), (param)) : 0)
+       ((smu)->ppt_funcs->send_smc_msg_with_param? (smu)->ppt_funcs->send_smc_msg_with_param((smu), (msg), (param)) : 0)
 #define smu_read_smc_arg(smu, arg) \
-       ((smu)->funcs->read_smc_arg? (smu)->funcs->read_smc_arg((smu), (arg)) : 0)
+       ((smu)->ppt_funcs->read_smc_arg? (smu)->ppt_funcs->read_smc_arg((smu), (arg)) : 0)
 #define smu_alloc_dpm_context(smu) \
        ((smu)->ppt_funcs->alloc_dpm_context ? (smu)->ppt_funcs->alloc_dpm_context((smu)) : 0)
 #define smu_init_display_count(smu, count) \
-       ((smu)->funcs->init_display_count ? (smu)->funcs->init_display_count((smu), (count)) : 0)
+       ((smu)->ppt_funcs->init_display_count ? (smu)->ppt_funcs->init_display_count((smu), (count)) : 0)
 #define smu_feature_set_allowed_mask(smu) \
-       ((smu)->funcs->set_allowed_mask? (smu)->funcs->set_allowed_mask((smu)) : 0)
+       ((smu)->ppt_funcs->set_allowed_mask? (smu)->ppt_funcs->set_allowed_mask((smu)) : 0)
 #define smu_feature_get_enabled_mask(smu, mask, num) \
-       ((smu)->funcs->get_enabled_mask? (smu)->funcs->get_enabled_mask((smu), (mask), (num)) : 0)
+       ((smu)->ppt_funcs->get_enabled_mask? (smu)->ppt_funcs->get_enabled_mask((smu), (mask), (num)) : 0)
 #define smu_is_dpm_running(smu) \
        ((smu)->ppt_funcs->is_dpm_running ? (smu)->ppt_funcs->is_dpm_running((smu)) : 0)
 #define smu_notify_display_change(smu) \
-       ((smu)->funcs->notify_display_change? (smu)->funcs->notify_display_change((smu)) : 0)
+       ((smu)->ppt_funcs->notify_display_change? (smu)->ppt_funcs->notify_display_change((smu)) : 0)
 #define smu_store_powerplay_table(smu) \
        ((smu)->ppt_funcs->store_powerplay_table ? (smu)->ppt_funcs->store_powerplay_table((smu)) : 0)
 #define smu_check_powerplay_table(smu) \
@@ -107,19 +107,19 @@
        ((smu)->ppt_funcs->set_default_od8_settings ? (smu)->ppt_funcs->set_default_od8_settings((smu)) : 0)
 
 #define smu_get_current_clk_freq(smu, clk_id, value) \
-       ((smu)->funcs->get_current_clk_freq? (smu)->funcs->get_current_clk_freq((smu), (clk_id), (value)) : 0)
+       ((smu)->ppt_funcs->get_current_clk_freq? (smu)->ppt_funcs->get_current_clk_freq((smu), (clk_id), (value)) : 0)
 
 #define smu_tables_init(smu, tab) \
        ((smu)->ppt_funcs->tables_init ? (smu)->ppt_funcs->tables_init((smu), (tab)) : 0)
 #define smu_set_thermal_fan_table(smu) \
        ((smu)->ppt_funcs->set_thermal_fan_table ? (smu)->ppt_funcs->set_thermal_fan_table((smu)) : 0)
 #define smu_start_thermal_control(smu) \
-       ((smu)->funcs->start_thermal_control? (smu)->funcs->start_thermal_control((smu)) : 0)
+       ((smu)->ppt_funcs->start_thermal_control? (smu)->ppt_funcs->start_thermal_control((smu)) : 0)
 #define smu_stop_thermal_control(smu) \
-       ((smu)->funcs->stop_thermal_control? (smu)->funcs->stop_thermal_control((smu)) : 0)
+       ((smu)->ppt_funcs->stop_thermal_control? (smu)->ppt_funcs->stop_thermal_control((smu)) : 0)
 
 #define smu_smc_read_sensor(smu, sensor, data, size) \
-       ((smu)->funcs->read_sensor? (smu)->funcs->read_sensor((smu), (sensor), (data), (size)) : -EINVAL)
+       ((smu)->ppt_funcs->read_sensor? (smu)->ppt_funcs->read_sensor((smu), (sensor), (data), (size)) : -EINVAL)
 
 #define smu_pre_display_config_changed(smu) \
        ((smu)->ppt_funcs->pre_display_config_changed ? (smu)->ppt_funcs->pre_display_config_changed((smu)) : 0)
@@ -157,14 +157,14 @@
 
 
 #define smu_store_cc6_data(smu, st, cc6_dis, pst_dis, pst_sw_dis) \
-       ((smu)->funcs->store_cc6_data ? (smu)->funcs->store_cc6_data((smu), (st), (cc6_dis), (pst_dis), (pst_sw_dis)) : 0)
+       ((smu)->ppt_funcs->store_cc6_data ? (smu)->ppt_funcs->store_cc6_data((smu), (st), (cc6_dis), (pst_dis), (pst_sw_dis)) : 0)
 
 #define smu_get_dal_power_level(smu, clocks) \
-       ((smu)->funcs->get_dal_power_level ? (smu)->funcs->get_dal_power_level((smu), (clocks)) : 0)
+       ((smu)->ppt_funcs->get_dal_power_level ? (smu)->ppt_funcs->get_dal_power_level((smu), (clocks)) : 0)
 #define smu_get_perf_level(smu, designation, level) \
-       ((smu)->funcs->get_perf_level ? (smu)->funcs->get_perf_level((smu), (designation), (level)) : 0)
+       ((smu)->ppt_funcs->get_perf_level ? (smu)->ppt_funcs->get_perf_level((smu), (designation), (level)) : 0)
 #define smu_get_current_shallow_sleep_clocks(smu, clocks) \
-       ((smu)->funcs->get_current_shallow_sleep_clocks ? (smu)->funcs->get_current_shallow_sleep_clocks((smu), (clocks)) : 0)
+       ((smu)->ppt_funcs->get_current_shallow_sleep_clocks ? (smu)->ppt_funcs->get_current_shallow_sleep_clocks((smu), (clocks)) : 0)
 
 #define smu_dpm_set_uvd_enable(smu, enable) \
        ((smu)->ppt_funcs->dpm_set_uvd_enable ? (smu)->ppt_funcs->dpm_set_uvd_enable((smu), (enable)) : 0)
@@ -180,10 +180,10 @@
 #define smu_get_thermal_temperature_range(smu, range) \
        ((smu)->ppt_funcs->get_thermal_temperature_range? (smu)->ppt_funcs->get_thermal_temperature_range((smu), (range)) : 0)
 #define smu_register_irq_handler(smu) \
-       ((smu)->funcs->register_irq_handler ? (smu)->funcs->register_irq_handler(smu) : 0)
+       ((smu)->ppt_funcs->register_irq_handler ? (smu)->ppt_funcs->register_irq_handler(smu) : 0)
 
 #define smu_get_dpm_ultimate_freq(smu, param, min, max) \
-               ((smu)->funcs->get_dpm_ultimate_freq ? (smu)->funcs->get_dpm_ultimate_freq((smu), (param), (min), (max)) : 0)
+               ((smu)->ppt_funcs->get_dpm_ultimate_freq ? (smu)->ppt_funcs->get_dpm_ultimate_freq((smu), (param), (min), (max)) : 0)
 
 #define smu_asic_set_performance_level(smu, level) \
        ((smu)->ppt_funcs->set_performance_level? (smu)->ppt_funcs->set_performance_level((smu), (level)) : -EINVAL);
@@ -193,10 +193,10 @@
                ((smu)->ppt_funcs->get_dpm_clk_limited ? (smu)->ppt_funcs->get_dpm_clk_limited((smu), (clk_type), (dpm_level), (freq)) : -EINVAL)
 
 #define smu_set_soft_freq_limited_range(smu, clk_type, min, max) \
-               ((smu)->funcs->set_soft_freq_limited_range ? (smu)->funcs->set_soft_freq_limited_range((smu), (clk_type), (min), (max)) : -EINVAL)
+               ((smu)->ppt_funcs->set_soft_freq_limited_range ? (smu)->ppt_funcs->set_soft_freq_limited_range((smu), (clk_type), (min), (max)) : -EINVAL)
 
 #define smu_override_pcie_parameters(smu) \
-               ((smu)->funcs->override_pcie_parameters ? (smu)->funcs->override_pcie_parameters((smu)) : 0)
+               ((smu)->ppt_funcs->override_pcie_parameters ? (smu)->ppt_funcs->override_pcie_parameters((smu)) : 0)
 
 #define smu_update_pcie_parameters(smu, pcie_gen_cap, pcie_width_cap) \
                ((smu)->ppt_funcs->update_pcie_parameters ? (smu)->ppt_funcs->update_pcie_parameters((smu), (pcie_gen_cap), (pcie_width_cap)) : 0)

diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index b621ff328c06d22ef18a5d7f9554e57dc6ec13b1..bbb74b1d5d8016bcd01122b3fdf93d0d10292381 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -33,9 +33,6 @@
 #include "smu_v11_0.h"
 #include "soc15_common.h"
 #include "atom.h"
-#include "vega20_ppt.h"
-#include "arcturus_ppt.h"
-#include "navi10_ppt.h"
 #include "amd_pcie.h"
 
 #include "asic_reg/thm/thm_11_0_2_offset.h"
@@ -63,7 +60,7 @@ static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu,
        return 0;
 }
 
-static int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg)
+int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg)
 {
        struct amdgpu_device *adev = smu->adev;
 
@@ -90,7 +87,7 @@ static int smu_v11_0_wait_for_response(struct smu_context *smu)
        return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
 }
 
-static int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg)
+int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg)
 {
        struct amdgpu_device *adev = smu->adev;
        int ret = 0, index = 0;
@@ -115,7 +112,7 @@ static int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg)
 
 }
 
-static int
+int
 smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
                              uint32_t param)
 {
@@ -146,7 +143,7 @@ smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
        return ret;
 }
 
-static int smu_v11_0_init_microcode(struct smu_context *smu)
+int smu_v11_0_init_microcode(struct smu_context *smu)
 {
        struct amdgpu_device *adev = smu->adev;
        const char *chip_name;
@@ -208,7 +205,7 @@ out:
        return err;
 }
 
-static int smu_v11_0_load_microcode(struct smu_context *smu)
+int smu_v11_0_load_microcode(struct smu_context *smu)
 {
        struct amdgpu_device *adev = smu->adev;
        const uint32_t *src;
@@ -246,7 +243,7 @@ static int smu_v11_0_load_microcode(struct smu_context *smu)
        return 0;
 }
 
-static int smu_v11_0_check_fw_status(struct smu_context *smu)
+int smu_v11_0_check_fw_status(struct smu_context *smu)
 {
        struct amdgpu_device *adev = smu->adev;
        uint32_t mp1_fw_flags;
@@ -261,7 +258,7 @@ static int smu_v11_0_check_fw_status(struct smu_context *smu)
        return -EIO;
 }
 
-static int smu_v11_0_check_fw_version(struct smu_context *smu)
+int smu_v11_0_check_fw_version(struct smu_context *smu)
 {
        uint32_t if_version = 0xff, smu_version = 0xff;
        uint16_t smu_major;
@@ -356,7 +353,7 @@ static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table,
        return 0;
 }
 
-static int smu_v11_0_setup_pptable(struct smu_context *smu)
+int smu_v11_0_setup_pptable(struct smu_context *smu)
 {
        struct amdgpu_device *adev = smu->adev;
        const struct smc_firmware_header_v1_0 *hdr;
@@ -435,7 +432,7 @@ static int smu_v11_0_fini_dpm_context(struct smu_context *smu)
        return 0;
 }
 
-static int smu_v11_0_init_smc_tables(struct smu_context *smu)
+int smu_v11_0_init_smc_tables(struct smu_context *smu)
 {
        struct smu_table_context *smu_table = &smu->smu_table;
        struct smu_table *tables = NULL;
@@ -462,7 +459,7 @@ static int smu_v11_0_init_smc_tables(struct smu_context *smu)
        return 0;
 }
 
-static int smu_v11_0_fini_smc_tables(struct smu_context *smu)
+int smu_v11_0_fini_smc_tables(struct smu_context *smu)
 {
        struct smu_table_context *smu_table = &smu->smu_table;
        int ret = 0;
@@ -482,7 +479,7 @@ static int smu_v11_0_fini_smc_tables(struct smu_context *smu)
        return 0;
 }
 
-static int smu_v11_0_init_power(struct smu_context *smu)
+int smu_v11_0_init_power(struct smu_context *smu)
 {
        struct smu_power_context *smu_power = &smu->smu_power;
 
@@ -500,7 +497,7 @@ static int smu_v11_0_init_power(struct smu_context *smu)
        return 0;
 }
 
-static int smu_v11_0_fini_power(struct smu_context *smu)
+int smu_v11_0_fini_power(struct smu_context *smu)
 {
        struct smu_power_context *smu_power = &smu->smu_power;
 
@@ -577,7 +574,7 @@ int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
        return 0;
 }
 
-static int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
+int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
 {
        int ret, index;
        struct amdgpu_device *adev = smu->adev;
@@ -674,7 +671,7 @@ static int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
        return 0;
 }
 
-static int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
+int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
 {
        struct smu_table_context *smu_table = &smu->smu_table;
        struct smu_table *memory_pool = &smu_table->memory_pool;
@@ -720,7 +717,7 @@ static int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
        return ret;
 }
 
-static int smu_v11_0_check_pptable(struct smu_context *smu)
+int smu_v11_0_check_pptable(struct smu_context *smu)
 {
        int ret;
 
@@ -728,7 +725,7 @@ static int smu_v11_0_check_pptable(struct smu_context *smu)
        return ret;
 }
 
-static int smu_v11_0_parse_pptable(struct smu_context *smu)
+int smu_v11_0_parse_pptable(struct smu_context *smu)
 {
        int ret;
 
@@ -752,7 +749,7 @@ static int smu_v11_0_parse_pptable(struct smu_context *smu)
        return ret;
 }
 
-static int smu_v11_0_populate_smc_pptable(struct smu_context *smu)
+int smu_v11_0_populate_smc_pptable(struct smu_context *smu)
 {
        int ret;
 
@@ -761,7 +758,7 @@ static int smu_v11_0_populate_smc_pptable(struct smu_context *smu)
        return ret;
 }
 
-static int smu_v11_0_write_pptable(struct smu_context *smu)
+int smu_v11_0_write_pptable(struct smu_context *smu)
 {
        struct smu_table_context *table_context = &smu->smu_table;
        int ret = 0;
@@ -772,7 +769,7 @@ static int smu_v11_0_write_pptable(struct smu_context *smu)
        return ret;
 }
 
-static int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
+int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
 {
        int ret;
 
@@ -784,7 +781,7 @@ static int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t cl
        return ret;
 }
 
-static int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
+int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
 {
        struct smu_table_context *table_context = &smu->smu_table;
 
@@ -793,14 +790,10 @@ static int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
        if (!table_context)
                return -EINVAL;
 
-       if (smu->funcs->set_deep_sleep_dcefclk)
-               return smu->funcs->set_deep_sleep_dcefclk(smu,
-                               table_context->boot_values.dcefclk / 100);
-
-       return 0;
+       return smu_v11_0_set_deep_sleep_dcefclk(smu, table_context->boot_values.dcefclk / 100);
 }
 
-static int smu_v11_0_set_tool_table_location(struct smu_context *smu)
+int smu_v11_0_set_tool_table_location(struct smu_context *smu)
 {
        int ret = 0;
        struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
@@ -818,7 +811,7 @@ static int smu_v11_0_set_tool_table_location(struct smu_context *smu)
        return ret;
 }
 
-static int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
+int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
 {
        int ret = 0;
 
@@ -830,7 +823,7 @@ static int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
 }
 
 
-static int smu_v11_0_set_allowed_mask(struct smu_context *smu)
+int smu_v11_0_set_allowed_mask(struct smu_context *smu)
 {
        struct smu_feature *feature = &smu->smu_feature;
        int ret = 0;
@@ -857,7 +850,7 @@ failed:
        return ret;
 }
 
-static int smu_v11_0_get_enabled_mask(struct smu_context *smu,
+int smu_v11_0_get_enabled_mask(struct smu_context *smu,
                                      uint32_t *feature_mask, uint32_t num)
 {
        uint32_t feature_mask_high = 0, feature_mask_low = 0;
@@ -886,7 +879,7 @@ static int smu_v11_0_get_enabled_mask(struct smu_context *smu,
        return ret;
 }
 
-static int smu_v11_0_system_features_control(struct smu_context *smu,
+int smu_v11_0_system_features_control(struct smu_context *smu,
                                             bool en)
 {
        struct smu_feature *feature = &smu->smu_feature;
@@ -912,7 +905,7 @@ static int smu_v11_0_system_features_control(struct smu_context *smu,
        return ret;
 }
 
-static int smu_v11_0_notify_display_change(struct smu_context *smu)
+int smu_v11_0_notify_display_change(struct smu_context *smu)
 {
        int ret = 0;
 
@@ -970,7 +963,7 @@ smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
        return ret;
 }
 
-static int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
+int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
 {
        struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks;
        int ret = 0;
@@ -1050,7 +1043,7 @@ static int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
        return 0;
 }
 
-static int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
+int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
 {
        int ret = 0;
 
@@ -1078,7 +1071,7 @@ static int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
        return 0;
 }
 
-static int smu_v11_0_get_current_clk_freq(struct smu_context *smu,
+int smu_v11_0_get_current_clk_freq(struct smu_context *smu,
                                          enum smu_clk_type clk_id,
                                          uint32_t *value)
 {
@@ -1157,7 +1150,7 @@ static int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
        return 0;
 }
 
-static int smu_v11_0_start_thermal_control(struct smu_context *smu)
+int smu_v11_0_start_thermal_control(struct smu_context *smu)
 {
        int ret = 0;
        struct smu_temperature_range range;
@@ -1199,7 +1192,7 @@ static int smu_v11_0_start_thermal_control(struct smu_context *smu)
        return ret;
 }
 
-static int smu_v11_0_stop_thermal_control(struct smu_context *smu)
+int smu_v11_0_stop_thermal_control(struct smu_context *smu)
 {
        struct amdgpu_device *adev = smu->adev;
 
@@ -1232,7 +1225,7 @@ static int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
 
 }
 
-static int smu_v11_0_read_sensor(struct smu_context *smu,
+int smu_v11_0_read_sensor(struct smu_context *smu,
                                 enum amd_pp_sensors sensor,
                                 void *data, uint32_t *size)
 {
@@ -1269,7 +1262,7 @@ static int smu_v11_0_read_sensor(struct smu_context *smu,
        return ret;
 }
 
-static int
+int
 smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
                                        struct pp_display_clock_request
                                        *clock_req)
@@ -1322,7 +1315,7 @@ failed:
        return ret;
 }
 
-static int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
+int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
 {
        int ret = 0;
        struct amdgpu_device *adev = smu->adev;
@@ -1347,7 +1340,7 @@ static int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
        return ret;
 }
 
-static uint32_t
+uint32_t
 smu_v11_0_get_fan_control_mode(struct smu_context *smu)
 {
        if (!smu_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
@@ -1387,7 +1380,7 @@ smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
        return 0;
 }
 
-static int
+int
 smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
 {
        struct amdgpu_device *adev = smu->adev;
@@ -1416,7 +1409,7 @@ smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
        return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
 }
 
-static int
+int
 smu_v11_0_set_fan_control_mode(struct smu_context *smu,
                               uint32_t mode)
 {
@@ -1444,7 +1437,7 @@ smu_v11_0_set_fan_control_mode(struct smu_context *smu,
        return ret;
 }
 
-static int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
+int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
                                       uint32_t speed)
 {
        struct amdgpu_device *adev = smu->adev;
@@ -1473,7 +1466,7 @@ static int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
 #define XGMI_STATE_D0 1
 #define XGMI_STATE_D3 0
 
-static int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
+int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
                                     uint32_t pstate)
 {
        int ret = 0;
@@ -1526,7 +1519,7 @@ static const struct amdgpu_irq_src_funcs smu_v11_0_irq_funcs =
        .process = smu_v11_0_irq_process,
 };
 
-static int smu_v11_0_register_irq_handler(struct smu_context *smu)
+int smu_v11_0_register_irq_handler(struct smu_context *smu)
 {
        struct amdgpu_device *adev = smu->adev;
        struct amdgpu_irq_src *irq_src = smu->irq_source;
@@ -1558,7 +1551,7 @@ static int smu_v11_0_register_irq_handler(struct smu_context *smu)
        return ret;
 }
 
-static int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
+int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
                struct pp_smu_nv_clock_table *max_clocks)
 {
        struct smu_table_context *table_context = &smu->smu_table;
@@ -1588,7 +1581,7 @@ static int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
        return 0;
 }
 
-static int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
+int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
 {
        int ret = 0;
 
@@ -1602,7 +1595,7 @@ static int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu, enum smu_v
        return smu_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq);
 }
 
-static bool smu_v11_0_baco_is_support(struct smu_context *smu)
+bool smu_v11_0_baco_is_support(struct smu_context *smu)
 {
        struct amdgpu_device *adev = smu->adev;
        struct smu_baco_context *smu_baco = &smu->smu_baco;
@@ -1626,7 +1619,7 @@ static bool smu_v11_0_baco_is_support(struct smu_context *smu)
        return false;
 }
 
-static enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
+enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
 {
        struct smu_baco_context *smu_baco = &smu->smu_baco;
        enum smu_baco_state baco_state;
@@ -1638,7 +1631,7 @@ static enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
        return baco_state;
 }
 
-static int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
+int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
 {
 
        struct smu_baco_context *smu_baco = &smu->smu_baco;
@@ -1662,7 +1655,7 @@ out:
        return ret;
 }
 
-static int smu_v11_0_baco_reset(struct smu_context *smu)
+int smu_v11_0_baco_reset(struct smu_context *smu)
 {
        int ret = 0;
 
@@ -1683,7 +1676,7 @@ static int smu_v11_0_baco_reset(struct smu_context *smu)
        return ret;
 }
 
-static int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
+int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
                                                 uint32_t *min, uint32_t *max)
 {
        int ret = 0, clk_id = 0;
@@ -1718,7 +1711,7 @@ failed:
        return ret;
 }
 
-static int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
+int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
                            uint32_t min, uint32_t max)
 {
        int ret = 0, clk_id = 0;
@@ -1747,7 +1740,7 @@ static int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum s
        return ret;
 }
 
-static int smu_v11_0_override_pcie_parameters(struct smu_context *smu)
+int smu_v11_0_override_pcie_parameters(struct smu_context *smu)
 {
        struct amdgpu_device *adev = smu->adev;
        uint32_t pcie_gen = 0, pcie_width = 0;
@@ -1787,79 +1780,3 @@ static int smu_v11_0_override_pcie_parameters(struct smu_context *smu)
        return ret;
 
 }
-
-
-static const struct smu_funcs smu_v11_0_funcs = {
-       .init_microcode = smu_v11_0_init_microcode,
-       .load_microcode = smu_v11_0_load_microcode,
-       .check_fw_status = smu_v11_0_check_fw_status,
-       .check_fw_version = smu_v11_0_check_fw_version,
-       .send_smc_msg = smu_v11_0_send_msg,
-       .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
-       .read_smc_arg = smu_v11_0_read_arg,
-       .setup_pptable = smu_v11_0_setup_pptable,
-       .init_smc_tables = smu_v11_0_init_smc_tables,
-       .fini_smc_tables = smu_v11_0_fini_smc_tables,
-       .init_power = smu_v11_0_init_power,
-       .fini_power = smu_v11_0_fini_power,
-       .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
-       .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
-       .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
-       .check_pptable = smu_v11_0_check_pptable,
-       .parse_pptable = smu_v11_0_parse_pptable,
-       .populate_smc_tables = smu_v11_0_populate_smc_pptable,
-       .write_pptable = smu_v11_0_write_pptable,
-       .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
-       .set_tool_table_location = smu_v11_0_set_tool_table_location,
-       .init_display_count = smu_v11_0_init_display_count,
-       .set_allowed_mask = smu_v11_0_set_allowed_mask,
-       .get_enabled_mask = smu_v11_0_get_enabled_mask,
-       .system_features_control = smu_v11_0_system_features_control,
-       .notify_display_change = smu_v11_0_notify_display_change,
-       .set_power_limit = smu_v11_0_set_power_limit,
-       .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
-       .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
-       .start_thermal_control = smu_v11_0_start_thermal_control,
-       .stop_thermal_control = smu_v11_0_stop_thermal_control,
-       .read_sensor = smu_v11_0_read_sensor,
-       .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
-       .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
-       .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
-       .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
-       .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
-       .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
-       .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
-       .gfx_off_control = smu_v11_0_gfx_off_control,
-       .register_irq_handler = smu_v11_0_register_irq_handler,
-       .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
-       .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
-       .baco_is_support = smu_v11_0_baco_is_support,
-       .baco_get_state = smu_v11_0_baco_get_state,
-       .baco_set_state = smu_v11_0_baco_set_state,
-       .baco_reset = smu_v11_0_baco_reset,
-       .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
-       .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
-       .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
-};
-
-void smu_v11_0_set_smu_funcs(struct smu_context *smu)
-{
-       struct amdgpu_device *adev = smu->adev;
-
-       smu->funcs = &smu_v11_0_funcs;
-       switch (adev->asic_type) {
-       case CHIP_VEGA20:
-               vega20_set_ppt_funcs(smu);
-               break;
-       case CHIP_ARCTURUS:
-               arcturus_set_ppt_funcs(smu);
-               break;
-       case CHIP_NAVI10:
-       case CHIP_NAVI14:
-       case CHIP_NAVI12:
-               navi10_set_ppt_funcs(smu);
-               break;
-       default:
-               pr_warn("Unknown asic for smu11\n");
-       }
-}

diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
index 92e1c0a3f428d41f404f289d363e37b80c861d5f..139dd737eaa5c5d5cf13747a1db1a2764a513525 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
@@ -30,7 +30,6 @@
 #include "smu_v12_0.h"
 #include "soc15_common.h"
 #include "atom.h"
-#include "renoir_ppt.h"
 
 #include "asic_reg/mp/mp_12_0_0_offset.h"
 #include "asic_reg/mp/mp_12_0_0_sh_mask.h"
@@ -42,7 +41,7 @@
 #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK          0x00000006L
 #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT        0x1
 
-static int smu_v12_0_send_msg_without_waiting(struct smu_context *smu,
+int smu_v12_0_send_msg_without_waiting(struct smu_context *smu,
                                              uint16_t msg)
 {
        struct amdgpu_device *adev = smu->adev;
@@ -51,7 +50,7 @@ static int smu_v12_0_send_msg_without_waiting(struct smu_context *smu,
        return 0;
 }
 
-static int smu_v12_0_read_arg(struct smu_context *smu, uint32_t *arg)
+int smu_v12_0_read_arg(struct smu_context *smu, uint32_t *arg)
 {
        struct amdgpu_device *adev = smu->adev;
 
@@ -59,7 +58,7 @@ static int smu_v12_0_read_arg(struct smu_context *smu, uint32_t *arg)
        return 0;
 }
 
-static int smu_v12_0_wait_for_response(struct smu_context *smu)
+int smu_v12_0_wait_for_response(struct smu_context *smu)
 {
        struct amdgpu_device *adev = smu->adev;
        uint32_t cur_value, i;
@@ -78,7 +77,7 @@ static int smu_v12_0_wait_for_response(struct smu_context *smu)
        return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
 }
 
-static int smu_v12_0_send_msg(struct smu_context *smu, uint16_t msg)
+int smu_v12_0_send_msg(struct smu_context *smu, uint16_t msg)
 {
        struct amdgpu_device *adev = smu->adev;
        int ret = 0, index = 0;
@@ -103,7 +102,7 @@ static int smu_v12_0_send_msg(struct smu_context *smu, uint16_t msg)
 
 }
 
-static int
+int
 smu_v12_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
                              uint32_t param)
 {
@@ -133,7 +132,7 @@ smu_v12_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
        return ret;
 }
 
-static int smu_v12_0_check_fw_status(struct smu_context *smu)
+int smu_v12_0_check_fw_status(struct smu_context *smu)
 {
        struct amdgpu_device *adev = smu->adev;
        uint32_t mp1_fw_flags;
@@ -148,7 +147,7 @@ static int smu_v12_0_check_fw_status(struct smu_context *smu)
        return -EIO;
 }
 
-static int smu_v12_0_check_fw_version(struct smu_context *smu)
+int smu_v12_0_check_fw_version(struct smu_context *smu)
 {
        uint32_t if_version = 0xff, smu_version = 0xff;
        uint16_t smu_major;
@@ -182,7 +181,7 @@ static int smu_v12_0_check_fw_version(struct smu_context *smu)
        return ret;
 }
 
-static int smu_v12_0_powergate_sdma(struct smu_context *smu, bool gate)
+int smu_v12_0_powergate_sdma(struct smu_context *smu, bool gate)
 {
        if (!(smu->adev->flags & AMD_IS_APU))
                return 0;
@@ -193,7 +192,7 @@ static int smu_v12_0_powergate_sdma(struct smu_context *smu, bool gate)
                return smu_send_smc_msg(smu, SMU_MSG_PowerUpSdma);
 }
 
-static int smu_v12_0_powergate_vcn(struct smu_context *smu, bool gate)
+int smu_v12_0_powergate_vcn(struct smu_context *smu, bool gate)
 {
        if (!(smu->adev->flags & AMD_IS_APU))
                return 0;
@@ -204,7 +203,7 @@ static int smu_v12_0_powergate_vcn(struct smu_context *smu, bool gate)
                return smu_send_smc_msg(smu, SMU_MSG_PowerUpVcn);
 }
 
-static int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable)
+int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable)
 {
        if (!(smu->adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
                return 0;
@@ -225,7 +224,7 @@ static int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable)
  * Returns 2=Not in GFXOFF.
  * Returns 3=Transition into GFXOFF.
  */
-static uint32_t smu_v12_0_get_gfxoff_status(struct smu_context *smu)
+uint32_t smu_v12_0_get_gfxoff_status(struct smu_context *smu)
 {
        uint32_t reg;
        uint32_t gfxOff_Status = 0;
@@ -238,7 +237,7 @@ static uint32_t smu_v12_0_get_gfxoff_status(struct smu_context *smu)
        return gfxOff_Status;
 }
 
-static int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable)
+int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable)
 {
        int ret = 0, timeout = 500;
 
@@ -262,7 +261,7 @@ static int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable)
        return ret;
 }
 
-static int smu_v12_0_init_smc_tables(struct smu_context *smu)
+int smu_v12_0_init_smc_tables(struct smu_context *smu)
 {
        struct smu_table_context *smu_table = &smu->smu_table;
        struct smu_table *tables = NULL;
@@ -280,7 +279,7 @@ static int smu_v12_0_init_smc_tables(struct smu_context *smu)
        return smu_tables_init(smu, tables);
 }
 
-static int smu_v12_0_fini_smc_tables(struct smu_context *smu)
+int smu_v12_0_fini_smc_tables(struct smu_context *smu)
 {
        struct smu_table_context *smu_table = &smu->smu_table;
 
@@ -296,7 +295,7 @@ static int smu_v12_0_fini_smc_tables(struct smu_context *smu)
        return 0;
 }
 
-static int smu_v12_0_populate_smc_tables(struct smu_context *smu)
+int smu_v12_0_populate_smc_tables(struct smu_context *smu)
 {
        struct smu_table_context *smu_table = &smu->smu_table;
        struct smu_table *table = NULL;
@@ -311,7 +310,7 @@ static int smu_v12_0_populate_smc_tables(struct smu_context *smu)
        return smu_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
 }
 
-static int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
+int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
                                                 uint32_t *min, uint32_t *max)
 {
        int ret = 0;
@@ -389,11 +388,11 @@ failed:
        return ret;
 }
 
-static int smu_v12_0_mode2_reset(struct smu_context *smu){
+int smu_v12_0_mode2_reset(struct smu_context *smu){
        return smu_v12_0_send_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, SMU_RESET_MODE_2);
 }
 
-static int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
+int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
                            uint32_t min, uint32_t max)
 {
        int ret = 0;
@@ -446,36 +445,3 @@ static int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum s
 
        return ret;
 }
-
-static const struct smu_funcs smu_v12_0_funcs = {
-       .check_fw_status = smu_v12_0_check_fw_status,
-       .check_fw_version = smu_v12_0_check_fw_version,
-       .powergate_sdma = smu_v12_0_powergate_sdma,
-       .powergate_vcn = smu_v12_0_powergate_vcn,
-       .send_smc_msg = smu_v12_0_send_msg,
-       .send_smc_msg_with_param = smu_v12_0_send_msg_with_param,
-       .read_smc_arg = smu_v12_0_read_arg,
-       .set_gfx_cgpg = smu_v12_0_set_gfx_cgpg,
-       .gfx_off_control = smu_v12_0_gfx_off_control,
-       .init_smc_tables = smu_v12_0_init_smc_tables,
-       .fini_smc_tables = smu_v12_0_fini_smc_tables,
-       .populate_smc_tables = smu_v12_0_populate_smc_tables,
-       .get_dpm_ultimate_freq = smu_v12_0_get_dpm_ultimate_freq,
-       .mode2_reset = smu_v12_0_mode2_reset,
-       .set_soft_freq_limited_range = smu_v12_0_set_soft_freq_limited_range,
-};
-
-void smu_v12_0_set_smu_funcs(struct smu_context *smu)
-{
-       struct amdgpu_device *adev = smu->adev;
-
-       smu->funcs = &smu_v12_0_funcs;
-
-       switch (adev->asic_type) {
-       case CHIP_RENOIR:
-               renoir_set_ppt_funcs(smu);
-               break;
-       default:
-               pr_warn("Unknown asic for smu12\n");
-       }
-}

diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index f077db127d0412c30b7bf3cf5d476fae120aaae1..7c8933f987d1511134e28f6379b055a9612d56e6 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -2248,7 +2248,7 @@ vega20_notify_smc_dispaly_config(struct smu_context *smu)
        if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
                clock_req.clock_type = amd_pp_dcef_clock;
                clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
-               if (!smu->funcs->display_clock_voltage_request(smu, &clock_req)) {
+               if (!smu_v11_0_display_clock_voltage_request(smu, &clock_req)) {
                        if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
                                ret = smu_send_smc_msg_with_param(smu,
                                                                  SMU_MSG_SetMinDeepSleepDcefclk,
@@ -3031,7 +3031,7 @@ static int vega20_read_sensor(struct smu_context *smu,
                *size = 4;
                break;
        default:
-               ret = smu_smc_read_sensor(smu, sensor, data, size);
+               ret = smu_v11_0_read_sensor(smu, sensor, data, size);
        }
        mutex_unlock(&smu->sensor_lock);
 
@@ -3212,7 +3212,56 @@ static const struct pptable_funcs vega20_ppt_funcs = {
        .set_watermarks_table = vega20_set_watermarks_table,
        .get_thermal_temperature_range = vega20_get_thermal_temperature_range,
        .set_df_cstate = vega20_set_df_cstate,
-       .update_pcie_parameters = vega20_update_pcie_parameters
+       .update_pcie_parameters = vega20_update_pcie_parameters,
+       .init_microcode = smu_v11_0_init_microcode,
+       .load_microcode = smu_v11_0_load_microcode,
+       .init_smc_tables = smu_v11_0_init_smc_tables,
+       .fini_smc_tables = smu_v11_0_fini_smc_tables,
+       .init_power = smu_v11_0_init_power,
+       .fini_power = smu_v11_0_fini_power,
+       .check_fw_status = smu_v11_0_check_fw_status,
+       .setup_pptable = smu_v11_0_setup_pptable,
+       .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
+       .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
+       .check_pptable = smu_v11_0_check_pptable,
+       .parse_pptable = smu_v11_0_parse_pptable,
+       .populate_smc_tables = smu_v11_0_populate_smc_pptable,
+       .check_fw_version = smu_v11_0_check_fw_version,
+       .write_pptable = smu_v11_0_write_pptable,
+       .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
+       .set_tool_table_location = smu_v11_0_set_tool_table_location,
+       .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
+       .system_features_control = smu_v11_0_system_features_control,
+       .send_smc_msg = smu_v11_0_send_msg,
+       .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
+       .read_smc_arg = smu_v11_0_read_arg,
+       .init_display_count = smu_v11_0_init_display_count,
+       .set_allowed_mask = smu_v11_0_set_allowed_mask,
+       .get_enabled_mask = smu_v11_0_get_enabled_mask,
+       .notify_display_change = smu_v11_0_notify_display_change,
+       .set_power_limit = smu_v11_0_set_power_limit,
+       .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
+       .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
+       .start_thermal_control = smu_v11_0_start_thermal_control,
+       .stop_thermal_control = smu_v11_0_stop_thermal_control,
+       .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
+       .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
+       .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
+       .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
+       .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
+       .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
+       .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
+       .gfx_off_control = smu_v11_0_gfx_off_control,
+       .register_irq_handler = smu_v11_0_register_irq_handler,
+       .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
+       .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
+       .baco_is_support= smu_v11_0_baco_is_support,
+       .baco_get_state = smu_v11_0_baco_get_state,
+       .baco_set_state = smu_v11_0_baco_set_state,
+       .baco_reset = smu_v11_0_baco_reset,
+       .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
+       .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
+       .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
 };
 
 void vega20_set_ppt_funcs(struct smu_context *smu)