powerpc: slightly improve cache helpers

Cache instructions (dcbz, dcbi, dcbf and dcbst) take two registers
that are summed to obtain the target address. Using 'Z' constraint
and '%y0' argument gives GCC the opportunity to use both registers
instead of only one with the second being forced to 0.

Suggested-by: Segher Boessenkool <segher@kernel.crashing.org>
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>

diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h
index 40ea5b3781c630b153952fe89541c1f6dc9cec9e..df8e4c407366e4ba386a8912d4817721b7ebde7b 100644 (file)
--- a/arch/powerpc/include/asm/cache.h
+++ b/arch/powerpc/include/asm/cache.h
@@ -85,22 +85,22 @@ extern void _set_L3CR(unsigned long);
 
 static inline void dcbz(void *addr)
 {
-       __asm__ __volatile__ ("dcbz 0, %0" : : "r"(addr) : "memory");
+       __asm__ __volatile__ ("dcbz %y0" : : "Z"(*(u8 *)addr) : "memory");
 }
 
 static inline void dcbi(void *addr)
 {
-       __asm__ __volatile__ ("dcbi 0, %0" : : "r"(addr) : "memory");
+       __asm__ __volatile__ ("dcbi %y0" : : "Z"(*(u8 *)addr) : "memory");
 }
 
 static inline void dcbf(void *addr)
 {
-       __asm__ __volatile__ ("dcbf 0, %0" : : "r"(addr) : "memory");
+       __asm__ __volatile__ ("dcbf %y0" : : "Z"(*(u8 *)addr) : "memory");
 }
 
 static inline void dcbst(void *addr)
 {
-       __asm__ __volatile__ ("dcbst 0, %0" : : "r"(addr) : "memory");
+       __asm__ __volatile__ ("dcbst %y0" : : "Z"(*(u8 *)addr) : "memory");
 }
 #endif /* !__ASSEMBLY__ */
 #endif /* __KERNEL__ */