riscv: dts: microchip: add missing CAN bus clocks

The CAN controller on PolarFire SoC has an AHB peripheral clock _and_ a
CAN bus clock. The bus clock was omitted when the binding was written,
but is required for operation. Make up for lost time and add to the DT.

Fixes: 38a71fc04895 ("riscv: dts: microchip: add mpfs's CAN controllers")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
index 59fd2d4ea523b8a6f6a4c63ed098d8bb3032c00c..c2b334a64be5c18be4f3704fd447e1c7a9885e50 100644 (file)
--- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
@@ -422,7 +422,7 @@
                can0: can@2010c000 {
                        compatible = "microchip,mpfs-can";
                        reg = <0x0 0x2010c000 0x0 0x1000>;
-                       clocks = <&clkcfg CLK_CAN0>;
+                       clocks = <&clkcfg CLK_CAN0>, <&clkcfg CLK_MSSPLL3>;
                        interrupt-parent = <&plic>;
                        interrupts = <56>;
                        status = "disabled";
@@ -431,7 +431,7 @@
                can1: can@2010d000 {
                        compatible = "microchip,mpfs-can";
                        reg = <0x0 0x2010d000 0x0 0x1000>;
-                       clocks = <&clkcfg CLK_CAN1>;
+                       clocks = <&clkcfg CLK_CAN1>, <&clkcfg CLK_MSSPLL3>;
                        interrupt-parent = <&plic>;
                        interrupts = <57>;
                        status = "disabled";